TJA1041T/H/V,512 Datasheet TJA1041T/CM,118, TJA1041T/VM,518, TJA1041T/N1,518 | P7-P9

Product data sheet Rev. 06 — 5 December 2007 7 of 26

NXP Semiconductors

TJA1041

High speed CAN transceiver

7.1.3 Standby mode

The Standby mode is the ﬁrst-level power saving mode of the transceiver, offering reduced

current consumption. In Standby mode the transceiver is not able to transmit or receive

data and the low-power receiver is activated to monitor bus activity. The bus pins are

biased at ground level (via R

i(cm)

). Pin INH is still active, so voltage regulators controlled

by this pin INH will be active too.

Pins RXD and ERR will reﬂect any wake-up requests (provided that V

I/O

and V

are

present).

7.1.4 Go-to-sleep command mode

The go-to-sleep command mode is the controlled route for entering Sleep mode. In

go-to-sleep command mode the transceiver behaves as if in Standby mode, plus a

go-to-sleep command is issued to the transceiver. After remaining in go-to-sleep

command mode for the minimum hold time (t

h(min)

), the transceiver will enter Sleep mode.

The transceiver will not enter the Sleep mode if the state of pins STB or EN is changed or

the UV

BAT

, pwon or wake-up ﬂag is set before t

h(min)

has expired.

7.1.5 Sleep mode

The Sleep mode is the second-level power saving mode of the transceiver. Sleep mode is

entered via the go-to-sleep command mode, and also when the undervoltage detection

time on either V

or V

I/O

elapses before that voltage level has recovered. In Sleep mode

the transceiver still behaves as described for Standby mode, but now pin INH is set

ﬂoating. Voltage regulators controlled by pin INH will be switched off, and the current into

pin V

BAT

is reduced to a minimum. Waking up a node from Sleep mode is possible via the

wake-up ﬂag and (as long as the UV

NOM

ﬂag is not set) via pin STB.

7.2 Internal ﬂags

The TJA1041 makes use of seven internal ﬂags for its fail-safe fallback mode control and

system diagnosis support. Table 4 shows the relation between ﬂags and operating modes

of the transceiver. Five of the internal ﬂags can be made available to the controller via pin

ERR. Table 5 shows the details on how to access these ﬂags. The following sections

describe the seven internal ﬂags.

Table 5. Accessing internal ﬂags via pin ERR

Internal ﬂag Flag is available on pin ERR

[1]

Flag is cleared

NOM

no by setting the pwon or wake-up

ﬂag

BAT

no when V

BAT

has recovered

pwon in pwon/listen-only mode (coming from

Standby mode, go-to-sleep command mode,

or Sleep mode)

on entering normal mode

wake-up in Standby mode, go-to-sleep command

mode, and Sleep mode (provided that V

I/O

and V

are present)

on entering normal mode, or by

setting the pwon or UV

NOM

ﬂag

Product data sheet Rev. 06 — 5 December 2007 8 of 26

NXP Semiconductors

TJA1041

High speed CAN transceiver

[1] Pin ERR is an active-LOW output, so a LOW level indicates a set ﬂag and a HIGH level indicates a cleared

ﬂag. Allow pin ERR to stabilize for at least 8 µs after changing operating modes.

[2] Allow for a TXD dominant time of at least 4 µs per dominant-recessive cycle.

7.2.1 UV

NOM

ﬂag

NOM

is the V

and V

I/O

undervoltage detection ﬂag. The ﬂag is set when the voltage

on pin V

drops below V

CC(sleep)

for longer than t

UV(VCC)

or when the voltage on pin V

I/O

drops below V

I/O(sleep)

for longer than t

UV(VI/O)

. When the UV

NOM

ﬂag is set, the transceiver

will enter Sleep mode to save power and not disturb the bus. In Sleep mode the voltage

regulators connected to pin INH are disabled, avoiding the extra power consumption in

case of a short-circuit condition. After a waiting time (ﬁxed by the same timers used for

setting UV

NOM

) any wake-up request or setting of the pwon ﬂag will clear UV

NOM

and the

timers, allowing the voltage regulators to be reactivated at least until UV

NOM

is set again.

7.2.2 UV

BAT

ﬂag

BAT

is the V

BAT

undervoltage detection ﬂag. The ﬂag is set when the voltage on pin V

BAT

drops below V

BAT(stb)

. When UV

BAT

is set, the transceiver will try to enter Standby mode to

save power and not disturb the bus. UV

BAT

is cleared when the voltage on pin V

BAT

has

recovered. The transceiver will then return to the operating mode determined by the logic

state of pins STB and EN.

7.2.3 Pwon ﬂag

Pwon is the V

BAT

power-on ﬂag. This ﬂag is set when the voltage on pin V

BAT

has

recovered after it dropped below V

BAT(pwon)

, particularly after the transceiver was

disconnected from the battery. By setting the pwon ﬂag, the UV

NOM

ﬂag and timers are

cleared and the transceiver cannot enter Sleep mode. This ensures that any voltage

regulator connected to pin INH is activated when the node is reconnected to the battery. In

pwon/listen-only mode the pwon ﬂag can be made available on pin ERR. The ﬂag is

cleared when the transceiver enters normal mode.

7.2.4 Wake-up ﬂag

The wake-up ﬂag is set when the transceiver detects a local or a remote wake-up request.

A local wake-up request is detected when a logic state change on pin WAKE remains

stable for at least t

wake

. A remote wake-up request is detected when the bus remains in

dominant state for at least t

BUS

. The wake-up ﬂag can only be set in Standby mode,

go-to-sleep command mode or Sleep mode. Setting of the ﬂag is blocked during the

NOM

ﬂag waiting time. By setting the wake-up ﬂag, the UV

NOM

ﬂag and timers are

wake-up

source

in normal mode (before the fourth dominant to

recessive edge on pin TXD

[2]

)

on leaving normal mode, or by

setting the pwon ﬂag

bus failure in normal mode (after the fourth dominant to

recessive edge on pin TXD

[2]

on re-entering normal mode

local failure in pwon/listen-only mode (coming from

normal mode)

on entering normal mode or when

RXD is dominant while TXD is

recessive (provided that all local

failures are resolved)

Table 5. Accessing internal ﬂags via pin

ERR

…continued

Internal ﬂag Flag is available on pin ERR

[1]

Flag is cleared

Product data sheet Rev. 06 — 5 December 2007 9 of 26

NXP Semiconductors

TJA1041

High speed CAN transceiver

cleared. The wake-up ﬂag is immediately available on pins ERR and RXD (provided that

I/O

and V

are present). The ﬂag is cleared at power-on, or when the UV

NOM

ﬂag is set

or the transceiver enters normal mode.

7.2.5 Wake-up source ﬂag

Wake-up source recognition is provided via the wake-up source ﬂag, which is set when

the wake-up ﬂag is set by a local wake-up request via pin WAKE. The wake-up source ﬂag

can only be set after the pwon ﬂag is cleared. In normal mode the wake-up source ﬂag

can be made available on pin ERR. The ﬂag is cleared at power-on or when the

transceiver leaves normal mode.

7.2.6 Bus failure ﬂag

The bus failure ﬂag is set if the transceiver detects a bus line short-circuit condition to

BAT

, V

or GND during four consecutive dominant-recessive cycles on pin TXD, when

trying to drive the bus lines dominant. In normal mode the bus failure ﬂag can be made

available on pin ERR. The ﬂag is cleared when the transceiver re-enters normal mode.

7.2.7 Local failure ﬂag

In normal mode or pwon/listen-only mode the transceiver can recognize ﬁve different local

failures, and will combine them into one local failure ﬂag. The ﬁve local failures are: TXD

dominant clamping, RXD recessive clamping, a TXD-to-RXD short circuit, bus dominant

clamping, and overtemperature. The nature and detection of these local failures is

described in Section 7.3 “Local failures”. In pwon/listen-only mode the local failure ﬂag can

be made available on pin ERR. The ﬂag is cleared when entering normal mode or when

RXD is dominant while TXD is recessive, provided that all local failures are resolved.

7.3 Local failures

The TJA1041 can detect ﬁve different local failure conditions. Any of these failures will set

the local failure ﬂag, and in most cases the transmitter of the transceiver will be disabled.

The following sections give the details.

7.3.1 TXD dominant clamping detection

A permanent LOW level on pin TXD (due to a hardware or software application failure)

would drive the CAN bus into a permanent dominant state, blocking all network

communication. The TXD dominant time-out function prevents such a network lock-up by

disabling the transmitter of the transceiver if pin TXD remains at a LOW level for longer

than the TXD dominant time-out t

dom(TXD)

. The t

dom(TXD)

timer deﬁnes the minimum

possible bit rate of 40 kbit/s. The transmitter remains disabled until the local failure ﬂag is

cleared.

7.3.2 RXD recessive clamping detection

An RXD pin clamped to HIGH level will prevent the controller connected to this pin from

recognizing a bus dominant state. So the controller can start messages at any time, which

is likely to disturb all bus communication. RXD recessive clamping detection prevents this

effect by disabling the transmitter when the bus is in dominant state without RXD reﬂecting

this. The transmitter remains disabled until the local failure ﬂag is cleared.

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TJA1041T/H/V,512

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