MAX7347ATE+T Datasheet MAX7347AEE+, MAX7348AEP+, MAX7349AEG+ | P13-P15

MAX7347/MAX7348/MAX7349

2-Wire Interfaced Low-EMI Key Switch

and Sounder Controllers

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Command Address Autoincrementing

Address autoincrementing allows the MAX7347/

MAX7348/MAX7349 to be configured with fewer trans-

missions by minimizing the number of times the com-

mand address needs to be sent. The command

address stored in the MAX7347/MAX7348/MAX7349

generally increments after each data byte is written or

read (Table 4). Autoincrementing applies only to the

key-scan command addresses and not to the sounder

command addresses.

Registers Description

Initial Power-Up

On power-up, all control registers are reset and the

MAX7347/MAX7348/MAX7349 enter shutdown mode

(Tables 5, 6). Table 7 shows the register address map

for the key-scan section.

COMMAND ADDRESS

FUNCTION

D15 D14 D13 D12 D11 D10 D9 D8

ADDRESS

CODE

(hex)

Keys FIFO 000000000x00

Debounce 000000010x01

Autorepeat 000000100x02

Interrupt 000000110x03

Configuration 000001000x04

Ports 000001010x05

Key Sound 000001100x06

Alert Sound 000001110x07

Table 7. Key-Scan Register Address Map

ADDRESS

CODE

(hex)

D7 D6 D5 D4 D3 D2 D1 D0

KEYS FIFO REGISTER* 0X00

OVERFLOW

FLAG

KEY SWITCH THAT HAS BEEN

DEBOUNCED

FIFO has not overflowed 0x00 0 X X X X X X X

FIFO overflowed; FIFO contains the first eight

key events

0x00 1 X X X X X X X

This key is the last FIFO item (key-switch data

not zero)

0x00 X 0 X X X X X X

Key 0 was EITHER the last FIFO item OR the

FIFO is empty and no key has been pressed

0x00 0 0 0 0 0 0 0 0

This key is not the last FIFO item 0x00 X 1 X X X X X X

Power-up default setting 0x00 0 0 0 0 0000

Table 8. Keys FIFO Register Format

Reading the key-scan FIFO clears the INT. INT is only reasserted by a key event after the FIFO has been emptied by read(s).

MAX7347/MAX7348/MAX7349

2-Wire Interfaced Low-EMI Key Switch

and Sounder Controllers

14 ______________________________________________________________________________________

Key-Scan Registers

Eight key-scan registers are described in the following

sections.

Keys FIFO Register

The keys FIFO register contains the information pertain-

ing to the status of the keys FIFO, as well as the key-

press events that have been debounced (Table 8). Bits

D0 to D5 denote which of the 64 keys have been

debounced and the keys are numbered as in Table 2

and Figure 1. D6 indicates whether the present

debounced key is the last one in the FIFO, with 1

denoting that there are more keys after the present one,

and 0 denoting that the present debounced key is the

last one stored in the FIFO. D7 is the overflow flag,

which denotes whether the keys FIFO has overflowed.

Reading the key-scan FIFO clears the interrupt INT. INT

is only reasserted after the FIFO has been emptied by

performing enough read operations.

Debounce Register

The debounce register sets the time for each debounce

cycle, as well as setting whether the GPO ports are

enabled or disabled. Bits D0 through D4 set the

debounce time in increments of 1ms starting at 9ms

and ending at 40ms (Table 9). Bits D5 through D7 set

which one of the GPO ports is to be enabled. Note that

not any port can be enabled at a particular time. The

GPO ports can be enabled only in the combinations

shown in Table 9, from all disabled to all enabled.

Autorepeat Register

The autorepeat register sets the autorepeat frequency

(repeat rate) and its delay. The autorepeat function allows

a key to be consecutively asserted when the key itself is

pressed down without being released. The autorepeat

delay specifies the delay between the first press and the

beginning of the autorepeating, provided that the key has

not been released. The autorepeat frequency specifies

how fast the continuously pressed-down key to be assert-

ed once autorepeating has started is. Bits D0 through D3

specify the autorepeat delay in terms of debounce cycles

ADDRESS CODE

(hex)

D7 D6 D5 D4 D3 D2 D1 D0

DEBOUNCE REGISTER 0x01

PORTS ENABLE DEBOUNCE TIME

Debounce time is 9ms 0x01 X X X 0000 0

Debounce time is 10ms 0x01 X X X 0000 1

Debounce time is 11ms 0x01 X X X 0001 0

Debounce time is 12ms 0x01 X X X 0001 1

All the way through to 0x01 X X X ———— —

Debounce time is 37ms 0x01 X X X 1110 0

Debounce time is 38ms 0x01 X X X 1110 1

Debounce time is 39ms 0x01 X X X 1111 0

Debounce time is 40ms 0x01 X X X 1111 1

GPO ports disabled (full key-scan functionality) 0x01 0 0 0 XXXX X

GPO port 7 enabled 0x01 0 0 1 XXXX X

GPO ports 7 and 6 enabled 0x01 0 1 0 XXXX X

GPO ports 7, 6, and 5 enabled 0x01 0 1 1 XXXX X

GPO ports 7, 6, 5, and 4 enabled 0x01 1 0 0 XXXX X

GPO ports 7, 6, 5, 4, and 3 enabled 0x01 1 0 1 XXXX X

GPO ports 7, 6, 5, 4, 3, and 2 enabled 0x01 1 1 XXXXX X

Power-up default setting 0x01 1 111111 1

Table 9. Debounce Register Format

MAX7347/MAX7348/MAX7349

ranging from 8 debounce cycles to 128 debounce cycles

(Table 10). Bits D4 through D6 specify the autorepeat

rate or frequency ranging from 4 to 32 debounce cycles.

Bit D7 specifies whether the auto-repeat function is

enabled with 0 denoting autorepeat disabled and 1

denoting autorepeat enabled.

Interrupt Register

The interrupt register contains information related to the

settings of the interrupt request function, as well as the

status of the INT output, which can also be configured

as a GPO. Bits D0 through D4 set the key-scan interrupt

frequency. By setting bits D0 through D4 to an appropri-

ate value, the interrupt can be asserted at the end of the

selected number of debounce cycles (Table 11). This

number ranges from 1 to 31 debounce cycles. If bits D0

through D4 are set to 00000, the INT output is config-

ured as a GPO that is controlled by bit D6 in the ports

INT status bits D5, D6, and D7 are still set and cleared in

the normal way at the end of each debounce cycle as if

bits D0 through D4 were set to 00001.

Bits D5 and D6 denote whether an interrupt was set

due to a key-scan event (bit D5) or to an alert event (bit

D6). Bit D7 represents whether an interrupt request has

been asserted with 0 denoting no INT asserted and 1

denoting that INT has been asserted.

The interrupt register is a read-only register and writes

to it are ignored. Reading the interrupt register does

clear an alert event INT, but does not clear a key-scan

event INT. An interrupt request caused by a key-scan

event(s) is cleared when the FIFO is emptied.

Configuration Register

The configuration register reflects the sounder status,

controls the I

C bus timeout feature, enables the alert

input interrupt feature, enables the sounder to respond

to both alert input and key debounce events, and con-

trols the shutdown of the device (Table 12).

Ports Register

The ports register sets the values of ports 2 through 7 and

the INT port when configured as GPOs. The settings in

this register are ignored for ports not configured as

GPOs, and a read from this register returns the values

stored in the register and not the actual port conditions

(Table 13). The ports register also serves to read the alert

input and this is done through bit D0 with a 0 denoting a

low on the alert input and a 1 denoting a high.

Key-Sound Register

The key-sound register specifies the duration and fre-

quency of the sound to be executed by the sounder con-

troller when a key or a set of keys are debounced if the

sounder output has been enabled to be set by a key

debounce event in the configuration register. When this

happens, the information of bits D7 through D1 is passed

on to the sounder register and the appropriate sound is

executed (Tables 14, 16). Least significant bit D0 is

ignored and always set to 1 when transferred to the

sounder register. See Table 16 for the format of setting

the frequency and duration of the sound to be executed.

If a key-sound register command is sent as 000xxxx

(continuous), then the command is stored as 111xxxx

(1000ms) in the sounder register.

Alert Sound Register

The alert sound register specifies the duration and fre-

quency of the sound to be executed by the sounder con-

troller at the falling edge of the alert input if the sounder

output has been enabled to be set by the alert input in

the configuration register. If this is the case, the informa-

tion of bits D7 through D1 is passed on to the sounder

15, 16). Least significant bit D0 is always set to 1 and

this value is ignored when transferred to the sounder

frequency and duration of the sound to be executed.

Note that if an alert sound register command is sent as

000xxxx (continuous), then the command is actually

stored as 111xxxx (1000ms) in the sounder register.

Sounder Register

The sounder register stores the frequencies and duration

of the sounds to be executed by the sounder, as well as

the state of its two-deep FIFO (Table 16). D0 denotes

whether another command is lined in the queue at any

given moment. A 0 in D0 denotes that the queue is empty

while a 1 denotes that there is another command. By writ-

ing 0 to D0, the present command is executed and the

queue is cleared. When sending a command that has a

D0 set to 1, the queue is checked and, if empty, the sent

command is added to it while, if full, the sent command

replaces the queued command.

Bits D0 and D1, when taken in conjunction, set the level

of the sounder output when configured as a GPO and

also control the autoloop function provided that the rest of

the bits (D7 through D2) are set to 0. When the sounder is

configured as a GPO, the levels of the output are set by

D1, a 0 denoting a low and a 1 denoting a high. When D0

is set to 1 and the rest of the bits are set to 0, D1 controls

the autoloop function as defined in Table 16.

Bits D7 through D1 control the frequency and duration of

the sounds to be executed by the sounder. These sounds

include the musical notes of the 5th octave plus some

notes from the 6th and 7th octaves as well. See Table 16.

2-Wire Interfaced Low-EMI Key Switch

and Sounder Controllers

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MAX7347ATE+T

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Manufacturer:

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Description:

Interface - Specialized Low-EMI Key Switch & Sounder Controller

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MAX7347ATE+T

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