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AD9889B/PCBZ

P1-P3P4-P6P7-P9P10-P12
AD9889B Data Sheet
A
B
C
D
E
F
G
J
H
K
10 8 7 6 3 2 19 5 4
BOTTOM VIEW
(Not to Scale)
06291-004
Figure 4. 76-Ball BGA Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Type
1
Description BGA LFCSP LQFP
D10, D9, C10,
C9, A10, B10,
A9, B9, A8, B8,
A7, B7, A6, B6,
A5, B5, A4, B4,
A3, B3, A2, B2,
A1, B1
39 to 47,
50 to 63, 2
50 to 58, 65 to
78, 2
D[23:0] I Video Data Input. Digital input in RGB or YCbCr format.
Supports CMOS logic levels from 1.8 V to 3.3 V.
D1 6 6 CLK I Video Clock Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
C2 3 3 DE I Data Enable Bit for Digital Video. Supports CMOS logic levels
from 1.8 V to 3.3 V.
C1 4 4 HSYNC I Horizontal Sync Input. Supports CMOS logic levels from
1.8 V to 3.3 V.
D2 5 5 VSYNC I Vertical Sync Input. Supports CMOS logic levels from 1.8 V
to 3.3 V.
J3 18 23 EXT_SWG I Sets Internal Reference Currents. Place 887 Ω resistor
(1% tolerance) between this pin and ground.
K3
20
25
HPD
I
Hot Plug Detect Signal. This indicates to the interface
whether the receiver is connected. Supports 1.8 V to 5.0 V
CMOS logic levels.
E2 7 7 S/PDIF I S/PDIF (Sony/Philips Digital Interface) Audio Input. This is
the audio input from a Sony/Philips digital interface.
Supports CMOS logic levels from 1.8 V to 3.3 V.
E1
8
8
MCLK
I
Audio Reference Clock. 128 × N × f
S
with N = 1, 2, 3, or 4.
Set to 128 × sampling frequency (f
S
), 256 × f
S
, 384 × f
S
, or
512 × f
S
. Supports 1.8 V to 3.3 V CMOS logic levels.
F2, F1, G2, G1 9 to 12 9 to 12 I
2
S[3:0] I I
2
S Audio Data Inputs. These represent the eight channels of
audio (two per input) available through I
2
S. Supports CMOS
logic levels from 1.8 V to 3.3 V.
H2 13 13 SCLK I I
2
S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
H1 14 14 LRCLK I Left/Right Channel Selection. Supports CMOS logic levels
from 1.8 V to 3.3 V.
J7
2
26
2
33
2
PD/A0 I Power-Down Control and I
2
C Address Selection. The I
2
C
address and the PD polarity are set by the PD/A0 pin state
when the supplies are applied to the AD9889B. Supports
1.8 V to 3.3 V CMOS logic levels.
K1, K2 21, 22 27, 28 TxC−/TxC+ O Differential Clock Output. Differential clock output at pixel
clock rate; supports TMDS logic level.
K10, J10 30, 31 37, 38 Tx2−/Tx2+ O Differential Output Channel 2. Differential output of the red
data at 10× the pixel clock rate; supports TMDS logic level.
Rev. B | Page 6 of 11
Data Sheet AD9889B
Pin No.
Mnemonic Type
1
Description BGA LFCSP LQFP
K7, K8 27, 28 34, 35 Tx1−/Tx1+ O Differential Output Channel 1. Differential output of the
green data at 10× the pixel clock rate; supports TMDS logic level.
K4, K5 24, 25 30, 31 Tx0−/Tx0+ O Differential Output Channel 0. Differential output of the blue
data at 10× the pixel clock rate; TMDS logic level.
H10 32 40 INT O Interrupt. Open drain. A 2 kΩ pull-up resistor to the
microcontroller I/O supply is recommended.
J2, J5, J8, K9
19, 23, 29
24, 29, 36, 41
AVDD P 1.8 V Power Supply for TMDS Outputs.
D5, D6, D7, E7
1, 48, 49
1, 61, 62, 63, 64
DVDD P 1.8 V Power Supply for Digital and I/O Power Supply. These
pins supply power to the digital logic and I/Os. They should
be filtered and as quiet as possible.
G4, G5, J1
15, 16, 17,
16, 19, 20, 21
PVDD P 1.8 V PLL Power Supply. The most sensitive portion of the
AD9889B is the clock generation circuitry. These pins provide
power to the clock PLL. The designer should provide quiet,
noise-free power to these pins.
D4, E4, F4, J4,
G6, J6, K6, F7,
G7, H9, J9
N/A
15, 17, 18, 22,
26, 32, 39, 42,
43, 59, 60, 79, 80
GND P Ground. The ground return for all circuitry on-chip. For best
practice, assemble the AD9889B on a single, solid ground
plane with careful attention given to ground current paths.
N/A 64, paddle
on bottom
side
N/A DGND P Digital Ground. The ground return for all circuitry on-chip.
For best practice, assemble the AD9889B on a single, solid
ground plane with careful attention given to ground
current paths.
F9 36 47 SDA C
3
Serial Port Data I/O. This pin serves as the serial port data I/O
slave for register access. Supports CMOS logic levels from
1.8 V to 3.3 V.
F10 35 46 SCL C
3
Serial Port Data Clock. This pin serves as the serial port data
clock slave for register access. Supports CMOS logic levels
from 1.8 V to 3.3 V.
E10 37 48 MDA C
3
Serial Port Data I/O Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
E9 38 49 MCL C
3
Serial Port Data Clock Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
G9 34 45 DDCSDA C
3
Serial Port Data I/O to Receiver. This pin serves as the master
to the DDC bus. Supports a 5 V CMOS logic level.
G10
33
44
DDCSCL
C
3
Serial Port Data Clock to Receiver. This pin serves as the
master clock for the DDC bus. Supports a 5 V CMOS logic level.
1
I = input, O = output, P = power supply, C = control.
2
Pin J7 (BGA), Pin 26 (LFCSP), and Pin 33 (LQFP) are dual function pins: I
2
C selection and power-down control. The I
2
C selection function occurs at power-up; the power-
down control function occurs whenever the state of the pin is changed from its original state at power-up.
3
For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from ATV_VideoTx_Apps@analog.com.
Rev. B | Page 7 of 11
AD9889B Data Sheet
Rev. B | Page 8 of 11
APPLICATIONS INFORMATION
DESIGN RESOURCES
Analog Devices, Inc. evaluation kits, reference design
schematics, and other support documentation are available
under the nondisclosure agreement (NDA) from
ATV_VideoTx_Apps@analog.com.
Other resources include:
EIA/CEA-861B, which describes audio and video infoframes as
well as the E-EDID structure for HDMI. It is available from
Consumer Electronics Association (CEA).
The HDMI v. 1.3, a defining document for HDMI Version 1.3,
and the HDMI Compliance Test Specification Version 1.3 are
available from HDMI Licensing, LLC.
The HDCP v. 1.2 is the defining document for HDCP
Version 1.2 available from Digital Content Protection, LLC.
DOCUMENT CONVENTIONS
In this data sheet, data is represented using the conventions
described in Table 4.
Table 4. Document Conventions
Data
Type
Format
0xNN
Hexadecimal (Base-16) numbers are represented using
the C language notation, preceded by 0x.
0bNN
Binary (Base-2) numbers are represented using the C
language notation, preceded by 0b.
NN
Decimal (Base-10) numbers are represented using no
additional prefixes or suffixes.
Bit
Bits are numbered in little endian format, that is, the
least significant bit of a byte or word is referred to as Bit 0.
P1-P3P4-P6P7-P9P10-P12

AD9889B/PCBZ

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