1
DATASHEET
Dual LDO with Low Noise, Very High PSRR and Low I
Q
ISL9000A
ISL9000A is a high performance dual LDO capable of sourcing
300mA current from each output. It has a low standby current
and very high PSRR and is stable with output capacitance of
1µF to 10µF with ESR of up to 200m.
The device integrates an individual Power-On-Reset (POR)
function for each output. The POR delay for VO2 can be
externally programmed by connecting a timing capacitor to the
CPOR pin. The POR delay for VO1 is internally fixed at
approximately 2ms. A reference bypass pin is also provided for
connecting a noise filtering capacitor for low noise and high-
PSRR applications.
The quiescent current is typically only 42µA with both LDO’s
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.
Several combinations of voltage outputs are standard. Output
voltage options for each LDO range from 1.5V to 3.3V. Other
output voltage options may be available upon request.
Features
Integrates two 300mA high performance LDOs
Excellent transient response to large current steps
±1.8% accuracy over all operating conditions
Excellent load regulation: < 0.1% voltage change across full
range of load current
Low output noise: typically 30µV
RMS
@ 100µA (1.5V)
Very high PSRR: 90dB @ 1kHz
Extremely low quiescent current: 42µA (both LDOs active)
Wide input voltage capability: 2.3V to 6.5V
Low dropout voltage: typically 200mV @ 300mA
Stable with 1µF to 10µF ceramic capacitors
Separate enable and POR pins for each LDO
Soft-start and staged turn-on to limit input current surge
during enable
Current limit and overheat protection
Tiny 10 Ld 3mmx3mm DFN package
-40°C to +85°C operating temperature range
Pb-free (RoHS compliant)
Applications
PDAs, Cell Phones and Smart Phones
Portable Instruments, MP3 Players
Handheld Devices including Medical Handheld
FIGURE 1. TYPICAL APPLICATION
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X7R CERAMIC CAPACITOR
ISL9000A
VIN
EN1
EN2
CBYP
CPOR
VO1
VO2
POR2
POR1
GND
10
9
8
7
6
1
2
3
4
5
VIN (2.3 TO 6.5V)
ENABLE1
ENABLE2
VO1
VO2
RESET1
RESET2
C1 C2 C3 C4 C5
C3: 0.01µF X7R CERAMIC CAPACITOR
OFF
ON
OFF
ON
(200ms DELAY,
C3 = 0.01µF)
(2ms DELAY)
VO2 TOO LOW
VO2 OK
VO1 TOO LOW
V
OUT1
OK
October 15, 2015
FN6391.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Copyright Intersil Americas LLC 2007, 2008, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9000A
2
FN6391.3
October 15, 2015
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Block Diagram
VO2
LDO
ERROR
AMPLIFIER
IS1 1VQEN1
LDO-1
LDO-2
POR
COMPARATOR
VOK1
POR1
VREF
TRIM
VIN
VO1
VO2
POR2
POR1
GND
EN2
EN1
CONTROL
LOGIC
POR2
DELAY
POR1
DELAY
VOLTAGE
REFERENCE
GENERATOR
BANDGAP AND
TEMPERATURE
SENSOR
UVLO
VOK2
VOK1
1.00V
0.94V
0.90V
IS1
IS2
QEN1
QEN2
VO1
VO2
100k100k
CPOR
CBYP
VO1
~1.0V
VOK2
POR2
ISL9000A
3
FN6391.3
October 15, 2015
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Pin Configuration
ISL9000A
(10 LD 3X3 DFN)
TOP VIEW
VIN
EN1
EN2
CBYP
CPOR
VO1
VO2
POR2
POR1
GND
2
3
4
1
5
9
8
7
10
6
Pin Descriptions
PIN
NUMBER
PIN
NAME TYPE DESCRIPTION
1 VIN Analog I/O Supply Voltage/LDO Input:
Connect a 1µF, X5R ceramic capacitor to GND.
2 EN1 Low Voltage Compatible
CMOS Input
LDO-1 Enable.
3 EN2 Low Voltage Compatible
CMOS Input
LDO-2 Enable.
4 CBYP Analog I/O Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
5 CPOR Analog I/O POR2 Delay Setting Capacitor Pin:
Connect a capacitor between this pin and GND to delay the POR2
output release after LDO-2
output reaches 94% of its specified voltage level. (200ms delay per 0.01µF).
6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane.
7POR1
Open Drain Output (1mA) Open-drain POR Output for LDO-1 (active-low):
Internally connected to VO1 through 100k resistor.
8POR2
Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low):
Internally connected to VO2 through 100k resistor.
9VO2
Analog I/O LDO-2 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
10 VO1 Analog I/O LDO-1 Output:
Connect capacitor of value 1µF to 10µF to GND (1µF recommended).

ISL9000AIRFCZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LDO Voltage Regulators W/ANNEAL LW NOISE HI PSRRLDO 10LD 3X3 5V/
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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