4
LT1713/LT1714
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CM
Input Voltage Range ● –5.1 5.1 V
CMRR Common Mode Rejection Ratio –5V ≤ V
CM
≤ 5V 62 70 dB
● 60 dB
PSRR
+
Positive Power Supply Rejection Ratio 2.4V ≤ V
+
≤ 7V, V
CM
= –5V 68 80 dB
● 65 dB
PSRR
–
Negative Power Supply Rejection Ratio –7V ≤ V
–
≤ 0V, V
CM
= 5V 65 80 dB
● 60 dB
A
V
Small-Signal Voltage Gain (Note 10) 1V ≤ V
OUT
≤ 4V, R
L
= ∞ 1.5 3 V/mV
V
OH
Output Voltage Swing HIGH (Note 8) I
OUT
= 1mA, V
OVERDRIVE
= 50mV ● 4.5 4.8 V
I
OUT
= 10mA, V
OVERDRIVE
= 50mV ● 4.3 4.6 V
V
OL
Output Voltage Swing LOW (Note 8) I
OUT
= –1mA, V
OVERDRIVE
= 50mV ● 0.20 0.4 V
I
OUT
= –10mA, V
OVERDRIVE
= 50mV ● 0.35 0.5 V
I
+
Positive Supply Current (Per Comparator) V
OVERDRIVE
= 1V 5.5 7.5 mA
● 9.0 mA
I
–
Negative Supply Current (Per Comparator) V
OVERDRIVE
= 1V 3.5 4.5 mA
● 5.0 mA
V
IH
Latch Pin High Input Voltage ● 2.4 V
V
IL
Latch Pin Low Input Voltage ● 0.8 V
I
IL
Latch Pin Current V
LATCH
= V
+
● 10 µA
t
PD
Propagation Delay (Note 6) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 7 10 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 20mV ● 12 ns
∆V
IN
= 100mV, V
OVERDRIVE
= 5mV 8.5 ns
∆t
PD
Differential Propagation Delay (Note 6) ∆V
IN
= 100mV, V
OVERDRIVE
= 20mV 0.5 3 ns
t
r
Output Rise Time 10% to 90% 4 ns
t
f
Output Fall Time 90% to 10% 4 ns
t
LPD
Latch Propagation Delay (Note 7) 8ns
t
SU
Latch Setup Time (Note 7) 1.5 ns
t
H
Latch Hold Time (Note 7) 0ns
t
DPW
Minimum Latch Disable Pulse Width (Note 7) 8 ns
f
MAX
Maximum Toggle Frequency V
IN
= 100mV
P-P
Sine Wave 65 MHz
t
JITTER
Output Timing Jitter V
IN
= 630mV
P-P
(0dBm) Sine Wave, f = 30MHz 15 ps
RMS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C.
V
+
= 5V, V
–
= –5V, V
CM
= 0V, V
LATCH
= 0.8V, C
LOAD
= 10pF, V
OVERDRIVE
= 20mV, unless otherwise specified.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1713C/LT1714C are guaranteed to meet specified
performance from 0°C to 70°C. They are designed, characterized and
expected to meet specified performance from –40°C to 85°C but are not
tested or QA sampled at these temperatures. The LT1713I/LT1714I are
guaranteed to meet specified performance from –40°C to 85°C.
Note 3: The negative supply should not be greater than the ground pin
voltages and the maximum voltage across the positive and negative
supplies should not be greater than 12V.
Note 4: Input offset voltage (V
OS
) is defined as the average of the two
voltages measured by forcing first one output, then the other to V
+
/2.
Note 5: Input bias current (I
B
) is defined as the average of the two input
currents.
Note 6: Propagation delay (t
PD
) is measured with the overdrive added to
the actual V
OS
. Differential propagation delay is defined as:
∆t
PD
= t
PD
+
– t
PD
–
. Load capacitance is 10pF. Due to test system
requirements, the LT1713/LT1714 propagation delay is specified with a
1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V
single supplies.
Note 7: Latch propagation delay (t
LPD
) is the delay time for the output to
respond when the latch pin is deasserted. Latch setup time (t
SU
) is the
interval in which the input signal must remain stable prior to asserting the
latch signal. Latch hold time (t
H
) is the interval after the latch is asserted in
which the input signal must remain stable. Latch disable pulse width
(t
DPW
) is the width of the negative pulse on the latch enable pin that
latches in new data on the data inputs.
