12
LT1713/LT1714
TYPICAL APPLICATIO S
U
Figure 4. Performance of Figure 3’s Circuit When
Operated Unidirectionally. Eye is Wide Open
171112 F04
Figure 5. Performance When Operated Simultaneous
Bidirectionally (Full Duplex). Crosstalk Appears as Noise.
Eye is Slightly Shut But Performance is Still Excellent
171112 F05
This amounts to an attenuation factor of 0.0978 with the
values shown. (The actual voltage on the lines will be cut
in half again due to the 120Ω Z
O
.) The reason this
attenuation factor is important is that it is the key to
deciding the ratio between the R2-R3 resistor divider in
the receiver path. This divider allows the receiver to reject
the large signal of the local transmitter and instead sense
the attenuated signal of the remote transmitter. Note that
in the above equations, R2 and R3 are not yet fully
determined because they only appear as a sum. This
allows the designer to now place an additional constraint
on their values. The R2-R3 divide ratio should be set to
equal half the attenuation factor mentioned above or:
R3/R2 = 1/2 • 0.0976
1
.
Having already designed R2 + R3 to be 2.653k (by allocat-
ing input impedance across R
O
, R1 and R2 + R3 to get the
requisite 120Ω), R2 and R3 then become 2529Ω and
123.5Ω respectively. The nearest 1% value for R2 is 2.55k
and that for R3 is 124Ω.
Voltage-Tunable Crystal Oscillator
The front page application is a variant of a basic crystal
oscillator that permits voltage tuning of the output fre-
quency. Such voltage-controlled crystal oscillators (VCXO)
are often employed where slight variation of a stable
carrier is required. This example is specifically intended to
provide a 4× NTSC sub-carrier tunable oscillator suitable
for phase locking.
The LT1713 is set up as a crystal oscillator. The varactor
diode is biased from the tuning input. The tuning network
is arranged so a 0V to 5V drive provides a reasonably
symmetric, broad tuning range around the 14.31818MHz
center frequency. The indicated selected capacitor sets
tuning bandwidth. It should be picked to complement loop
response in phase locking applications. Figure 6 is a plot
of tuning input voltage versus frequency deviation. Tuning
deviation from the 4× NTSC 14.31818MHz center fre-
quency exceeds ±240ppm for a 0V to 5V input.
1
Using the design value of R2 + R3 = 2.653k rather than the implementation value of 2.55k +
124Ω = 2.674k.
INPUT VOLTAGE (V)
0
FREQUENCY DEVIATION (kHz)
2
4
5
9
8
7
6
5
4
3
2
1
0
171112 F06
13
14.314.0MHz
14.31818MHz
14.3217MHz
Figure 6. Control Voltage vs Output Frequency for the First Page
Application Circuit. Tuning Deviation from Center Frequency
Exceeds ±240ppm
