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MC74VHCT86AM

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 3
1 Publication Order Number:
MC74VHCT86A/D
MC74VHCT86A
Quad 2-Input XOR Gate /
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHCT86A is an advanced high speed CMOS 2−input
Exclusive−OR gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic−level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic
to 3.0 V CMOS Logic while operating at the high−voltage power
supply.
The MC74VHCT86A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows it to be used to interface 5 V circuits to 3 V circuits. The output
structures also provide protection when V
CC
= 0 V. These input and
output structures help prevent device destruction caused by supply
voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
• High Speed: t
PD
= 4.8 ns (Typ) at V
CC
= 5 V
• Low Power Dissipation: I
CC
= 2 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• These Devices are Pb−Free and are RoHS Compliant
LOGIC DIAGRAM
Y = A)B
3
Y1
1
A1
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
14−LEAD SOIC
D SUFFIX
CASE 751A
http://onsemi.com
14−LEAD TSSOP
DT SUFFIX
CASE 948G
L
L
H
H
L
H
L
H
Inputs Output
AB
L
H
H
L
Y
FUNCTION TABLE
Device Package Shipping
ORDERING INFORMATION
MC74VHCT86ADR2G SOIC−14
(Pb−Free)
2500 / Tape &
Reel
MC74VHCT86ADTR2G TSSOP−14
(Pb−Free)
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
2500 / Tape &
Reel
MC74VHCT86A
http://onsemi.com
2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
out
DC Output Voltage V
CC
= 0
High or Low State
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
V
I
IK
Input Diode Current − 20 mA
I
OK
Output Diode Current (V
OUT
< GND; V
OUT
> V
CC
) ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Characteristics Symbol Min Max Unit
DC Supply Voltage V
CC
2.0 5.5 V
DC Input Voltage V
IN
0.0 5.5 V
DC Output Voltage V
CC
= 0
High or Low State
V
OUT
0.0
0.0
5.5
V
CC
V
Operating Temperature Range T
A
−55 +85 °C
Input Rise and Fall Time V
CC
= 3.3V ± 0.3V
V
CC
= 5.0V ± 0.5V
t
r
, t
f
0
0
100
20
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V, Measured in SOIC Package)
Symbol
Characteristic
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.3 0.8 V
V
OLV
Quiet Output Minimum Dynamic V
OL
− 0.3 − 0.8 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHCT86A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
V
CC
T
A
= 25°C T
A
≤ 85°C T
A
≤ 125°C
Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Unit
V
IH
Minimum High−Level
Input Voltage
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
V
IL
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= −50μA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= −4mA
I
OH
= −8mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50μA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 4mA
I
OL
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
I
IN
Maximum Input
Leakage Current
V
IN
= 5.5V or GND 0 to
5.5
±0.1 ±1.0 ±1.0 μA
I
CC
Maximum Quiescent
Supply Current
V
IN
= V
CC
or GND 5.5 2.0 20 40 μA
I
CCT
Quiescent Supply
Current
Input: V
IN
= 3.4V 5.5 1.35 1.50 1.65 mA
I
OPD
Output Leakage
Current
V
OUT
= 5.5V 0.0 0.5 5.0 10 μA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbol
Parameter Test Conditions
T
A
= 25°C T
A
= − 40 to 85°C
Uni
t
Min Typ Max Min Max
t
PLH
,
t
PHL
Propagation Delay,
A or B to Y
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
4.8
6.3
6.8
8.8
1.0
1.0
8.0
10.0
C
in
Input Capacitance 4 10 10 pF
C
PD
Power Dissipation Capacitance (Note 1)
Typical @ 25°C, V
CC
= 5.0V
pF
18
1. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/4 (per gate). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
3.0V
GND
50%
50% V
CC
A or B
Y
t
PHL
t
PLH
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 1. Switching Waveforms Figure 2. Test Circuit
V
OH
V
OL
P1-P3P4-P6

MC74VHCT86AM

Mfr. #:
Buy MC74VHCT86AM
Manufacturer:
ON Semiconductor
Description:
Logic Gates 2-5.5V Quad 2-Input
Lifecycle:
New from this manufacturer.
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