NLV14042BDG

MC14042B
http://onsemi.com
4
SWITCHING CHARACTERISTICS (Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol V
DD
Min
Typ
(Note 6)
Max Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time, D to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 135 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 57 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 35 ns
t
PLH
,
t
PHL
5.0
10
15
220
90
60
440
180
120
no
Propagation Delay Time, Clock to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 135 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 57 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 35 ns
t
PLH
,
t
PHL
5.0
10
15
220
90
60
440
180
120
ns
Clock Pulse Width t
WH
5.0
10
15
300
100
80
150
50
40
ns
Clock Pulse Rise and Fall Time t
TLH
,
t
THL
5.0
10
15
15
5.0
4.0
ms
Hold Time t
h
5.0
10
15
100
50
40
50
25
20
ns
Setup Time t
su
5.0
10
15
50
30
25
0
0
0
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14042B
http://onsemi.com
5
Figure 1. AC and Power Dissipation Test Circuit and Timing Diagram
(Data to Output)
V
DD
V
SS
PULSE
GENERATOR 1
16
5
6
4
7
13
14
CLOCK
POLARITY
D0
D1
D2
D3 Q
3
Q3
Q
2
Q2
Q1
Q1
Q
0
Q0
15
1
12
11
9
10
3
2
8
For Power Dissipation test, each output
is loaded with capacitance C
L
.
1
f
20 ns 20 ns
DATA INPUT
Q OUTPUT
Q
OUTPUT
t
PLH
t
PHL
t
TLH
t
THL
t
TLH
t
THL
90%
50%
10%
50%
90%
10%
90%
10%
50%
t
PHL
Figure 2. AC Test Circuit and Timing Diagram
(Clock to Output)
NOTE: C
L
connected to output under test.
20* ns 20 ns
90%
10%
PULSE
GENERATOR 1
PULSE
GENERATOR 2
V
DD
16
5
6
4
7
13
14
CLOCK
POLARITY
D0
D1
D2
D3 Q
3
Q3
Q
2
Q2
Q
1
Q1
Q
0
Q0
V
SS
8
15
1
12
11
9
10
3
2
50%
t
WH
20 ns
90%
50%
t
su
t
h
t
PLH
90%
50%
10%
CLOCK INPUT
P.G. 1
DATA INPUT
P.G. 2
Q OUTPUT
*Input clock rise time is 20 ns except for maximum rise time test.
MC14042B
http://onsemi.com
6
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B
S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X
1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
16
89
8X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
P
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MC14042B/D
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NLV14042BDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Latches QUAD Transprnt LATCH
Lifecycle:
New from this manufacturer.
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