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DG445DYZ-T

P1-P3P4-P6P7-P9P10-P12
1
®
FN3586.10
DG444, DG445
Monolithic, Quad SPST, CMOS Analog
Switches
The DG444 and DG445 monolithic CMOS analog switches
are drop-in replacements for the popular DG211 and DG212
series devices. They include four independent single pole
single throw (SPST) analog switches and TTL and CMOS
compatible digital inputs.
These switches feature lower analog ON resistance (<85Ω)
and faster switch time (t
ON
<250ns) compared to the DG211
and DG212. Charge injection has been reduced, simplifying
sample and hold applications.
The improvements in the DG444 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling ±20V signals when operating with ±20V power
supplies.
The four switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with
analog signals is quite low over a ±5V analog input range.
The switches in the DG444 and DG445 are identical,
differing only in the polarity of the selection logic.
Pinout
DG444, DG445
(16 LD SOIC, TSSOP)
TOP VIEW
Features
• ON Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 85Ω
• Low Power Consumption (P
D
) . . . . . . . . . . . . . . . <35μW
• Fast Switching Action
-t
ON
(Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
-t
OFF
(Max, DG444) . . . . . . . . . . . . . . . . . . . . . . . 140ns
• Low Charge Injection
• Upgrade from DG211, DG212
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN
1
D
1
S
1
V-
GND
S
4
IN
4
D
4
IN
2
S
2
V+
V
L
S
3
D
3
IN
3
D
2
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
DG444DY* DG444DY -40 to +85 16 Ld SOIC M16.15
DG444DYZ*
(Note)
DG444DYZ -40 to +85 16 Ld SOIC
(Pb-free)
M16.15
DG444DVZ*
(Note)
DG444DVZ -40 to +85 16 Ld TSSOP
(Pb-free)
M16.173
DG445DY* DG445DY -40 to +85 16 Ld SOIC M16.15
DG445DYZ*
(Note)
DG445DYZ -40 to +85 16 Ld SOIC
(Pb-free)
M16.15
DG445DVZ*
(Note)
DG445DVZ -40 to +85 16 Ld TSSOP
(Pb-free)
M16.173
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Data Sheet June 4, 2007
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999, 2003, 2004, 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
FN3586.10
June 4, 2007
Functional Diagrams
Schematic Diagram (One Channel)
TRUTH TABLE
LOGIC V
IN
DG444 DG445
0 ≤0.8V ON OFF
1 ≥2.4V OFF ON
S
1
D
1
S
2
D
2
S
3
D
3
S
4
D
4
IN
1
DG444
IN
2
IN
3
IN
4
S
1
D
1
S
2
D
2
S
3
D
3
S
4
D
4
IN
1
DG445
SWITCHES SHOWN FOR LOGIC “1” INPUT
IN
2
IN
3
IN
4
Pin Descriptions
PIN SYMBOL DESCRIPTION
1IN
1
Logic Control for Switch 1
2D
1
Drain (Output) Terminal for Switch 1
3S
1
Source (Input) Terminal for Switch 1
4 V- Negative Power Supply Terminal
5 GND Ground Terminal (Logic Common)
6S
4
Source (Input) Terminal for Switch 4
7D
4
Drain (Output) Terminal for Switch 4
8IN
4
Logic Control for Switch 4
9IN
3
Logic Control for Switch 3
10 D
3
Drain (Output) Terminal for Switch 3
11 S
3
Source (Input) Terminal for Switch 3
12 V
L
Logic Reference Voltage
13 V+ Positive Power Supply Terminal (Substrate)
14 S
2
Source (Input) Terminal for Switch 2
15 D
2
Drain (Output) Terminal for Switch 2
16 IN
2
Logic Control for Switch 2
S
D
V+
IN
X
GND
V-
V-
V+
V
L
DG444, DG445
3
FN3586.10
June 4, 2007
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
V
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) + 0.3V
Digital Inputs, V
S
, V
D
(Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns
Thermal Resistance (Typical, Note 2)
θ
JA
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Maximum Junction Temperature (Plastic Packages). . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Signals on S
X
, D
X
, or IN
X
exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, V
L
= 5V, V
IN
= 2.4V, 0.8V (Note 3),
Unless Otherwise Specified
PARAMETER TEST CONDITIONS
TEMP
(°C)
(NOTE 4)
MIN
(NOTE 5)
TYP
(NOTE 4)
MAX UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
ON
R
L
= 1kΩ, C
L
= 35pF, V
S
= ±10V
(Figure 1)
+25 - 120 250 ns
Turn-OFF Time, t
OFF
DG444 +25 - 110 140 ns
DG445 +25 - 160 210 ns
Charge Injection, Q (Figure 2) C
L
= 1nF, V
G
= 0V, R
G
= 0Ω +25 - -1 - pC
OFF Isolation (Figure 4) R
L
= 50Ω, C
L
= 5pF, f = 1MHz +25 - 60 - dB
Crosstalk (Channel-to-Channel)
(Figure 3)
+25 - -100 - dB
Source OFF Capacitance, C
S(OFF)
f = 1MHz, V
ANALOG
= 0 (Figure 5) +25 - 4 - pF
Drain OFF Capacitance, C
D(OFF)
+25 - 4 - pF
Channel ON Capacitance,
C
D(ON)
+ C
S(ON)
+25 - 16 - pF
DIGITAL INPUT CHARACTERISTICS
Input Current V
IN
Low, I
IL
V
IN
Under Test = 0.8V,
All Others = 2.4V
Full -0.5 -0.00001 0.5 μA
Input Current V
IN
High, I
IH
V
IN
Under Test = 2.4V,
All Others = 0.8V
Full -0.5 0.00001 0.5 μA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full -15 - 15 V
Drain-Source ON Resistance,
r
DS(ON)
I
S
= 10mA, V
D
= ±8.5V,
V+ = 13.5V, V- = -13.5V
+25 - 50 85 Ω
Full - - 100 Ω
Source OFF Leakage Current, I
S(OFF)
V+ = 16.5V, V- = -16.5V,
V
D
= ±15.5V, V
S
= 15.5V
+25 -0.5 0.01 0.5 nA
+85 -5 - 5 nA
DG444, DG445
P1-P3P4-P6P7-P9P10-P12

DG445DYZ-T

Mfr. #:
Buy DG445DYZ-T
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs SWITCH 4X SPST N O 16N IND
Lifecycle:
New from this manufacturer.
Delivery:
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