Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
http://www.cirrus.com
8-Pin, Stereo A/D Converter for Digital Audio
Features
Single +5 V Power Supply
18-Bit Resolution
94 dB Dynamic Range
Linear Phase Digital Anti-Alias Filtering
0.05 dB Passband Ripple
80 dB Stopband Rejection
Low Power Dissipation: 150 mW
Power-Down Mode for Portable
Applications
Complete CMOS Stereo A/D System
Delta-Sigma A/D Converters
Digital Anti-Alias Filtering
S/H Circuitry and Voltage Reference
Adjustable System Sampling Rates including
32, 44.1, and 48 kHz
General Description
The CS5330A/31A is a complete stereo analog-to-digi-
tal converter that performs antialias filtering, sampling
and analog-to-digital conversion generating 18-bit val-
ues for both left and right inputs in serial form. The
output sample rate can be infinitely adjusted between
2 kHz and 50 kHz.
The CS5330A/31A operates from a single +5 V supply
and requires only 150 mW for normal operation, making
it ideal for battery-powered applications.
The ADC uses delta-sigma modulation with 128X over-
sampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The linear-phase digital filter has a passband to
21.7 kHz, 0.05 dB passband ripple and >80 dB stop-
band rejection. The device also contains a high-pass fil-
ter to remove DC offsets.
The device is available in an 8-pin SOIC package in
both Commercial (
-10° to +70° C) and Automotive grades
(-40° to +85° C)
. Please refer to “Ordering Information” on
page 16 for complete details.
High
Pass
Filter
AINR
S/H
AGND
AINL
S/H
DAC
Serial Output Interface
Voltage Reference
Comparator
Comparator
LP Filter
LP Filter
VA+
SCLK
Digital Decimation
Filter
SDATA
MCLK
DAC
High
Pass
Filter
LRCK
8
5
6
423
1
7
Digital Decimation
Filter
MAY '11
DS138F6
CS5330A/31A
2 DS138F6
CS5330A/31A
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ................................................................................................................ 3
2. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
SPECIFIED OPERATING CONDITIONS................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
ANALOG INPUT CHARACTERISTICS.................................................................................... 5
DIGITAL CHARACTERISTICS................................................................................................. 6
DIGITAL FILTER CHARACTERISTICS ................................................................................... 6
SWITCHING CHARACTERISTICS .......................................................................................... 7
3. GENERAL DESCRIPTION ....................................................................................................... 9
3.1 System Design .................................................................................................................. 9
3.1.1 Master Clock ......................................................................................................... 9
3.1.2 Serial Data Interface ............................................................................................ 9
3.1.3 Master Mode ......................................................................................................... 9
3.1.4 Slave Mode ......................................................................................................... 10
3.1.5 CS5330A ............................................................................................................. 10
3.1.6 CS5331A ............................................................................................................. 10
3.1.7 Analog Connections ............................................................................................ 11
3.1.8 High-Pass Filter .................................................................................................. 11
3.1.9 Initialization and Power-Down ............................................................................. 11
3.1.10 Grounding and Power Supply Decoupling ........................................................ 12
3.1.11 Digital Filter ....................................................................................................... 13
4. PARAMETER DEFINITIONS .................................................................................................. 14
5. REFERENCES ........................................................................................................................ 15
6. PACKAGE DESCRIPTIONS .................................................................................................. 15
7. ORDERING INFORMATION ................................................................................................. 16
8. REVISION HISTORY .............................................................................................................. 16
LIST OF FIGURES
Figure 1. Typical Connection Diagram......................................................................................... 8
Figure 2. Data Output Timing-CS5330A .................................................................................... 10
Figure 3. Data Output Timing - CS5331A (I²S Compatible)....................................................... 10
Figure 4. CS5330A/31A Initialization and Power-Down Sequence............................................ 12
Figure 5. CS5330A/31A Digital Filter Stopband Rejection......................................................... 13
Figure 6. CS5330A/31A Digital Filter Transition Band ............................................................... 13
Figure 7. CS5330A/31A Digital Filter Passband Ripple ............................................................. 13
Figure 8. CS5330A/31A Digital Filter Transition Band ............................................................... 13
LIST OF TABLES
Table 1. Common Clock Frequencies......................................................................................... 9
DS138F6 3
CS5330A/31A
1. PIN DESCRIPTIONS
Pin Name
#
Pin Description
SDATA
1
Audio Serial Data Output (Output) - Two’s complement MSB-first serial data is output on this
pin. A 47 k resistor on this pin will place the CS5330A/31A into Master Mode.
SCLK
2
Serial Data Clock (Input/Output) - SCLK is an input clock at any frequency from 32x to 64x the
output word rate. SCLK can also be an output clock at 64x if in the Master Mode. Data is
clocked out on the falling edge of SCLK.
LRCK
3
Left/Right Clock (Input/Output) - LRCK selects the left or right channel for output on SDATA.
The LRCK frequency must be at the output sample rate. LRCK is an output clock if in Master
Mode. Although the outputs of each channel are transmitted at different times, the two words in
an LRCK cycle represent simultaneously sampled analog inputs.
MCLK
4
Master Clock Input (Input) - Source for the delta-sigma modulator sampling and digital filter
clock. Sample rates and digital filter characteristics scale to the MCLK frequency.
AINR
5
Analog Right Channel Input (Input) - Analog input for the right channel. Typically 4 Vpp for a
full-scale input signal.
AGND
6
Analog Ground (Input) - Analog ground reference.
VA+
7
Positive Analog Power (Input) - Positive analog supply (Nominally +5 V).
AINL
8
Analog Left Channel Input (Input) - Analog input for the left channel. Typically 4 Vpp for a full-
scale input signal.
72
63
54
81
S
ERIAL DATA OUTPUT
SERIAL DATA CLOCK
LEFT/RIGHT CLOCK
MASTER CLOCK
LEFT ANALOG INPUT
ANALOG POWER
ANALOG GROUND
RIGHT ANALOG INPU
T
SDATA
SCLK
LRCK
MCLK
AINL
VA+
AGND
AINR

CS5330A-BSZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs 8-Pin Stereo ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union