CS5330A-KSZ Datasheet CS5330A-BSZ, CS5330A-KSZ, CS5331A-DSZ | P10-P12

10 DS138F6

CS5330A/31A

3.1.4 Slave Mode

LRCK and SCLK become inputs in SLAVE mode. LRCK must be externally derived from MCLK and be

equal to Fs. The frequency of SCLK should be equal to 64xLRCK, though other frequencies are possible.

MCLK frequencies of 256x, 384x, and 512xFs are supported. The ratio of the applied MCLK to LRCK is

automatically detected during power-up and internal dividers are set to generate the appropriate internal

clocks.

3.1.5 CS5330A

The CS5330A data output format is shown in Figure 2. Notice that the MSB is clocked by the transition of

LRCK and the remaining seventeen data bits are clocked by the falling edge of SCLK. The data bits are

valid during the rising edge of SCLK.

3.1.6 CS5331A

The CS5331A data output format is shown in Figure 3. Notice the one SCLK period delay between the

LRCK transitions and the MSB of the data. The falling edges of SCLK cause the ADC to output the eigh-

teen data bits. The data bits are valid during the rising edge of SCLK. LRCK is also inverted compared to

the CS5330A interface. The CS5331A interface is compatible with I

18 19 20 21 22

31 0 1

19 20 21 22 23

31 0 1

SCLK

LRCK

Left Audio Data Right Audio Data

17 16

SDATA

17 17

Figure 2. Data Output Timing-CS5330A

18 19 20 21 22 31

19 20 21 22 23

31 0 1

SCLK

LRCK

Left Audio Data Right Audio Data

17 16

SDATA

Figure 3. Data Output Timing - CS5331A (I²S Compatible)

DS138F6 11

CS5330A/31A

3.1.7 Analog Connections

Figure 1 shows the analog input connections. The analog inputs are presented to the modulators via the

AINR and AINL pins. Each analog input will accept a maximum of 4 Vpp centered at +2.4 V.

The CS5330A/31A samples the analog inputs at 128 Fs, 6.144 MHz for a 48 kHz sample-rate. The dig-

ital filter rejects all noise above 29 kHz except for frequencies right around 6.144 MHz 21.7 kHz (and

multiples of 6.144 MHz). Most audio signals do not have significant energy at 6.144 MHz. Nevertheless,

a 150 resistor in series with each analog input and a 10 nF capacitor across the inputs will attenuate

any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modula-

tors. The use of capacitors which have a large voltage coefficient must be avoided since these will de-

grade signal linearity. It is also important that the self-resonant frequency of the capacitor be well above

the modulator sampling frequency. General purpose ceramics and film capacitors do not meet these re-

quirements. However, NPO and COG capacitors are acceptable. If active circuitry precedes the ADC, it

is recommended that the above RC filter is placed between the active circuitry and the AINR and AINL

pins. The above example frequencies scale linearly with Fs.

3.1.8 High-Pass Filter

The operational amplifiers in the input circuitry driving the CS5330A/31A may generate a small DC offset

into the A/D converter. The CS5330A/31A includes a high pass filter after the decimator to remove any

DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between

devices in a multichannel system.

The characteristics of this first-order high pass filter are outlined in the “Digital Filter Characteristics” on

page 6

3.1.9 Initialization and Power-Down

The Initialization and Power-Down sequence is shown in Figure 4. Upon initial power-up, the digital filters

and delta-sigma modulators are reset and the internal voltage reference is powered down. The device will

remain in the Initial Power-Down mode until MCLK is presented. Once MCLK is available, the

CS5330A/31A will make a master/slave mode decision based upon the presence/absence of a 47-k

pull-down resistor on SDATA as shown in Figure 1. The master/slave decision is made during initial pow-

er-up as shown in Figure 4.

In master mode, SCLK and LRCK are outputs where the MCLK/LRCK frequency ratio is 256x. LRCK will

appear as an output 127 MCLK cycles into the initialization sequence. At this time, power is applied to the

internal voltage reference and the analog inputs will move to approximately 2.4 Volts. SDATA is static low

during the initialization and high pass filter settling sequence, which requires 11,265 LRCK cycles (235

ms at a 48 kHz output sample rate).

In slave mode, SCLK and LRCK are inputs where the MCLK/LRCK frequency ratio must be either 256x,

384x,or 512x. Once the MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK

period to determine the MCLK/LRCK frequency ratio. At this time, power is applied to the internal voltage

reference and the analog inputs will move to approximately 2.4 Volts. SDATA is static high during the ini-

tialization and high pass filter settling sequence, which requires 11,265 LRCK cycles (235 ms at a 48 kHz

sample rate).

12 DS138F6

CS5330A/31A

The CS5330A and CS5331A have a Power-Down mode wherein typical consumption drops to 0.5 mW.

This is initiated when a loss of clock is detected on either the LRCK or MCLK pins in Slave Mode, or the

MCLK pin in Master Mode. The initialization sequence will begin when MCLK (and LRCK for slave mode)

are restored. In slave mode power-down, the CS5330A and CS5331A will adapt to changes in

MCLK/LRCK frequency ratio during the initialization sequence. It is recommended that clocks not be ap-

plied to the device prior to power supply settling. A reset circuit may be implemented by gating the MCLK

signal.

3.1.10 Grounding and Power Supply Decoupling

As with any high resolution converter, the ADC requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 1 shows the recommended power ar-

rangements with VA+ connected to a clean +5-V supply. Decoupling capacitors should be as near to the

ADC as possible, with the low value ceramic capacitor being the nearest. To minimize digital noise, con-

nect the ADC digital outputs only to CMOS inputs. The printed circuit board layout should have separate

analog and digital regions and ground planes. An evaluation board, CDB5330A or CDB5331A, is avail-

able which demonstrates the optimum layout and power supply arrangements, as well as allowing fast

evaluation of the CS5330A and CS5331A.

Figure 4. CS5330A/31A Initialization and Power-Down Sequence

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

CS5330A-KSZ

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Audio A/D Converter ICs IC 8-Pin Stereo ADC

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CS5330A-KSZ

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