ZL30132 Short Form Data Sheet
7
Zarlink Semiconductor Inc.
F2 tms I
u
Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
DD
. If this pin is not used
then it should be left unconnected.
Master Clock
H4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz
reference from a clock oscillator (XO) or crystal XTAL. The stability and accuracy
of the clock at this input determines the free-run accuracy and the long term
holdover stability of the output clocks.
H5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
Miscellaneous
F5 IC Internal Connection. Leave unconnected.
H6 IC Internal Connection. Connect to ground.
H7
D7
NC No Connection. Leave unconnected.
Power and Ground
C3
C8
E8
F6
F8
G6
H8
V
DD
P
P
P
P
P
P
P
Positive Supply Voltage. +3.3V
DC
nominal.
E6
F3
V
CORE
P
P
Positive Supply Voltage. +1.8V
DC
nominal.
B7
C4
AV
DD
P
P
Positive Analog Supply Voltage. +3.3V
DC
nominal.
B6
C7
F1
AV
CORE
P
P
P
Positive Analog Supply Voltage. +1.8V
DC
nominal.
D3
D4
D5
D6
E3
E4
E5
E7
F4
F7
V
SS
G
G
G
G
G
G
G
G
G
G
Ground. 0 Volts.
Pin # Name
I/O
Type
Description
