PCA8534A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 16 April 2015 38 of 53
NXP Semiconductors
PCA8534A
Automotive LCD driver for low multiplex rates
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCA8534A. Synchronization is guaranteed after a power-on reset. The only time that
SYNC
is likely to be needed is if synchronization is accidentally lost (for example, by noise
in adverse electrical environments or by defining a multiplex drive mode when PCA8534A
with different SA0 levels are cascaded).
SYNC
is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCA8534A asserts the SYNC
line at
the onset of its last active backplane signal and monitors the SYNC
line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCA8534A to assert
SYNC
. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCA8534A are shown in Figure 25
.
The contact resistance between the SYNC
on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
applicable to chip-on-glass applications. The maximum SYNC
contact resistance allowed
for the number of devices in cascade is given in Table 23
.
(1) Is master (OSC connected to V
SS
).
(2) Is slave (OSC connected to V
DD
).
Fig 24. Cascaded PCA8534A configuration
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