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RECEIVE MULTIFRAME BOUNDARY TIMING Figure 17
NOTES:
1. Low-high transitions on RMSYNC and RFSYNC occur one RCLK period early with respect to actual
frame and multiframe boundaries.
2. RAF transitions on true frame boundaries.
3. Delay from RPOS, RNEG to RSER is six RCLK periods.
4. RMSYNC and RCSYNC transition low on the falling edge of RFSYNC.
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RSR: RECEIVE STATUS REGISTER Figure 18
(MSB) (LSB)
RRA RDMA RSA1 RUA1 FSERR MFSERR RLOS ECS
SYMBOL POSITION NAME AND DESCRIPTION
RRA RSR.7 Receive Remote Alarm. Set when bit 3 of timeslot 0 in non-align
frames set for three consecutive non-align frames.
RDMA RSR.6 Receive Distant Multiframe Alarm. Set when bit 6 of timeslot 16
in frame 0 is set for three consecutive multiframes.
RSA1 RSR.5 Receive Signaling All Ones. Set when the contents of timeslot 16
have been all 1's for two consecutive frames.
RUA1 RSR.4 Receive Unframed All Ones. Set when less than three 0s have
been received in the last two consecutive frames.
FSERR RSR.3 Frame Resync Criteria Met. Set when the frame error criteria are
met; also the frame resync is initiated if RCR.1=0.
MFSERR RSR.2 CAS Multiframe Resync Criteria Met. Set when the CAS
multiframe error criteria are met; also, the frame resync is initiated
if RCR.1=0.
RLOS RSR.1 Receive Loss of Sync. Set when resync is in progress.
ECS RSR.0 Error Counter Saturation. Set when any of the on-chip counters
at FECR, CECR or BVCR saturates.
NOTE:
1. When in the CCS mode, the RDMA flag bit and the RDMA pin have no significance. It will be set
when bit 6 of timeslot 16 in frame 0 is set for three consecutive multiframes in either CAS or CCS
mode.
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RIMR: RECEIVE INTERRUPT MASK REGISTER Figure 19
(MSB) (LSB)
RRA RDMA RSA1 RUA1 FSERR MFSERR RLOS ECS
SYMBOL POSITION NAME AND DESCRIPTION
RRA RIMR.7
Receive Remote Alarm
1 = Interrupt enabled
0 = Interrupt masked
RDMA RIMR.6
Receive Distant Multiframe Alarm
1 = Interrupt enabled
0 = Interrupt masked
RSA1 RIMR.5
Receive Signaling All 1’s
1 = Interrupt enabled
0 = Interrupt masked
RUA1 RIMR.4
Receive Unframed All 1’s
1 = Interrupt enabled
0 = Interrupt masked
FSERR RIMR.3
Frame Resync Criteria Met
1 = Interrupt enabled
0 = Interrupt masked
MFSERR RIMR.2
CAS Multiframe Resync Criteria Met
1 = Interrupt enabled
0 = Interrupt masked
RLOS RIMR.1
Receive Loss of Sync
1 = Interrupt enabled
0 = Interrupt masked
ECS RIMR.0
Error Count Saturation
1 = Interrupt enabled
0 = Interrupt masked
ALARM REPORTING AND INTERRUPT SERVICING
Alarm and error conditions are reported at outputs and the RSR. Use of the RSR and error count registers
simplifies system error monitoring. The RSR can be read in one of two ways: a burst read does not
disturb the RSR contents; a direct read will clear all bits set in the RSR unless the alarm condition which
set them is still active. Interrupts are enabled via the RIMR and are generated whenever an alarm or error
condition sets an RSR bit. The host controller must service the transceiver in order to clear an interrupt
condition. Clearing the appropriate RIMR bit will unconditionally clear an interrupt.
BVCR: BIPOLAR VIOLATION COUNT REGISTER Figure 20
(MSB) (LSB)
BVD7 BVD6 BVD5 BVD4 BVD3 BVD2 BVD1 BVD0
SYMBOL POSITION NAME AND DESCRIPTION
BVD7 BVCR.7 MSB of bipolar violation count.
BVD0 BVCR.0 LSB of bipolar violation count.

DS2181AQ+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Network Controller & Processor ICs CEPT Primary Rate Transceive
Lifecycle:
New from this manufacturer.
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