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ISL6526ACBZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
10
FN9055.12
September 30, 2015
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Current Sinking
The ISL6526, ISL6526A incorporate a MOSFET shoot-through
protection method which allows a converter to sink current as
well as source current. Care should be exercised when
designing a converter with the ISL6526, ISL6526A when it is
known that the converter may sink current.
When the converter is sinking current, it is behaving as a
boost converter that is regulating its input voltage. This
means that the converter is boosting current into the input
rail of the regulator. If there is nowhere for this current to go,
(such as to other distributed loads on the rail or through a
voltage limiting protection device), the capacitance on this
rail will absorb the current. This situation will allow the
voltage level of the input rail to increase. If the voltage level
of the rail is boosted to a level that exceeds the maximum
voltage rating of any components attached to the input rail,
then those components may experience an irreversible
failure or experience stress that may shorten their lifespan.
Ensuring that there is a path for the current to flow other than
the capacitance on the rail will prevent this failure mode.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
300kHz or 600kHz, the resulting current transitions from one
device to another cause voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, radiate noise
into the circuit, and lead to device overvoltage stress.
Careful component layout and printed circuit board design
minimize the voltage spikes in the converters.
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET
and is picked up by the lower MOSFET. Any parasitic
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful component
selection, tight layout of the critical components, and short, wide
traces minimize the magnitude of voltage spikes.
There are two sets of critical components in a DC/DC
converter using the ISL6526, ISL6526A. The switching
components are the most critical because they switch large
amounts of energy, and therefore tend to generate large
amounts of noise. Next are the small signal components
which connect to sensitive nodes or supply critical bypass
current and signal coupling.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
converter. Note that capacitors C
IN
and C
OUT
could each
represent numerous physical capacitors. Dedicate one solid
layer (usually a middle layer of the PC board) for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
The switching components should be placed close to the
ISL6526, ISL6526A first. Minimize the length of the connections
between the input capacitors, C
IN
, and the power switches by
placing them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between the
upper MOSFET and lower MOSFET and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position the bypass capacitor, C
BP
, close to
the VCC pin with a via directly to the ground plane. Place the
PWM converter compensation components close to the FB
V
OUT
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
L
OUT
C
OUT
C
IN
+3.3V V
IN
KEY
COMP
ISL6526, ISL6526A
UGATE
R4
R
2
C
BP
FB
GND
CPVOUT
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
R
1
BOOT
C
2
VIA CONNECTION TO GROUND PLANE
LOAD
Q1
C
BOOT
PHASE
D1
R
3
C
3
C
1
Q2
LGATE
PHASE
VCC
C
VCC
ISL6526, ISL6526A
11
FN9055.12
September 30, 2015
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and COMP pins. The feedback resistors for both regulators
should also be located as close as possible to the relevant
FB pin with vias tied straight to the ground plane as required.
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a pulse
width modulated (PWM) wave with an amplitude of V
IN
at
the PHASE node. The PWM wave is smoothed by the output
filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at f
LC
and a zero at f
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6526, ISL6526A) and the impedance
networks Z
IN
and Z
FB
. The goal of the compensation
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f
0dB
) and adequate phase
margin. Phase margin is the difference between the closed
loop phase at f
0dB
and 180°. Equations 6, 7, 8 and 9 relate
the compensation network’s poles, zeros and gain to the
components (R
1
, R
2
, R
3
, C
1
, C
2
, and C
3
) in Figure 5. Use
these guidelines for locating the poles and zeros of the
compensation network:
1. Pick gain (R
2
/R
1
) for desired converter bandwidth.
2. Place first zero below filter’s double pole (~75% f
LC
).
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the previously mentioned guidelines
should give a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at f
P2
with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45°. Include worst case component variations when
determining phase margin.
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
1
C
2
COMP
V
OUT
FB
Z
FB
ISL6526, ISL6526A
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
f
LC
1
2 x L
O
x C
O
------------------------------------------=
(EQ. 4)
f
ESR
1
2 x ESR x C
O
-------------------------------------------=
(EQ. 5)
f
Z1
1
2 R
2
C
2
----------------------------------=
(EQ. 6)
f
Z2
1
2 x R
1
R
3
+ x C
3
-------------------------------------------------------=
(EQ. 7)
f
P1
1
2 x R
2
x
C
1
x C
2
C
1
C
2
+
----------------------



---------------------------------------------------------=
(EQ. 8)
f
P2
1
2 x R
3
x C
3
------------------------------------=
(EQ. 9)
ISL6526, ISL6526A
12
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September 30, 2015
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Component Selection Guidelines
Charge Pump Capacitor Selection
A capacitor across pins CT1 and CT2 is required to create
the proper bias voltage for the ISL6526, ISL6526A when
operating the IC from 3.3V. Selecting the proper capacitance
value is important so that the bias current draw and the
current required by the MOSFET gates do not overburden
the capacitor. A conservative approach is presented in
Equation 10.
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern digital ICs can produce high transient load slew
rates. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equations 11 and 12:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6526, ISL6526A will provide either 0% or 100% duty
cycle in response to a load transient. The response time is
the time required to slew the inductor current from an initial
current value to the transient current level. During this
interval, the difference between the inductor current and
the transient current level must be supplied by the output
capacitor. Minimizing the response time can minimize the
output capacitance required.
The response time to a transient is different for the
application of load and the removal of load. Equations 13
and 14 give the approximate response time interval for
application and removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
100
80
60
40
20
0
-20
-40
-60
f
P1
f
Z2
10M1M100k10k1k10010
OPEN LOOP
ERROR AMP GAIN
f
Z1
f
P2
f
LC
f
ESR
COMPENSATION
GAIN (dB)
FREQUENCY (Hz)
GAIN
MODULATOR
GAIN
LOOP GAIN
20
V
IN
V
OSC
------------------



log
20
R2
R1
--------


log
C
PUMP
I
BiasAndGate
V
CC
f
s
------------------------------------
1.5=
(EQ. 10)
I=
V
IN
- V
OUT
f
s
x L
V
OUT
V
IN
x
(EQ. 11)
V
OUT
= I x ESR
(EQ. 12)
t
RISE
=
L x I
TRAN
V
IN
- V
OUT
(EQ. 13)
t
FALL
=
L x I
TRAN
V
OUT
(EQ. 14)
ISL6526, ISL6526A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ISL6526ACBZ

Mfr. #:
Buy ISL6526ACBZ
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 600KHZ SNG PWM W/CHA RGE PUMP 14LD NSOIC
Lifecycle:
New from this manufacturer.
Delivery:
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