LTM8045
13
8045fc
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applicaTions inForMaTion
Setting Output Voltage
The output voltage is set by connecting a resistor (R
FB
)
from V
OUT
+
to the FB pin for a SEPIC and from V
OUT
to
the FB pin for an inverting converter. R
FB
is determined
from the equation R
FB
= [(V
OUT
– 1.215)/0.0833]kΩ for
a SEPIC and from R
FB
= [(|V
OUT
| + 0.005)/0.0833]kΩ for
an inverting converter.
Capacitor Selection Considerations
The C
IN
and C
OUT
capacitor values in Table 1 are the
minimum recommended values for the associated oper-
ating conditions
.
Applying capacitor values below those
indicated in Table 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap
-
plied voltage
and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application cir
-
cuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8045. A
ceramic input capacitor combined with trace or cable
inductance forms a high Q (under damped) tank circuit.
If the LTM8045 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possi
-
bly exceeding the device’s rating. This situation is easily
avoided; see the Hot-Plugging Safely section.
Programming Switching Frequency
The LTM8045 has an operational switching frequency range
between 200kHz and 2MHz. The free running frequency is
programmed with an external resistor from the RT pin to
ground. Do not leave this pin open under any circumstance.
When the SYNC pin is driven low (< 0.4V), the frequency
of operation is set by the resistor from RT to ground. The
R
T
value is calculated by the following equation:
R
T
=
91.9
f
OSC
1
where f
OSC
is the typical switching frequency in MHz and
R
T
is in kΩ.
Switching Frequency Trade-Offs
It is recommended that the user apply the optimal R
T
value
given in Table 1 for the corresponding input and output
operating condition. System level or other considerations,
however, may necessitate another operating frequency.
While the LTM8045 is flexible enough to accommodate a
wide range of operating frequencies, a haphazardly chosen
one may result in undesirable operation under certain op
-
erating or fault conditions. A frequency that is too high can
reduce
efficiency, generate excessive heat or even damage
the LTM8045 in some fault conditions. A frequency that
is too low can result in a final design that has too much
output ripple or too large of an output capacitor.
Switching Frequency Synchronization
The switching frequency can be synchronized to an external
clock source. To synchronize to the external source, simply
provide a digital clock signal at the SYNC pin. Switching
will occur at the SYNC clock frequency. Drive SYNC low
and the switching frequency will revert to the internal
free-running oscillator after a few clock periods.
Switching will stop if SYNC is driven high.
The duty cycle of
SYNC must be between 35% and 65%
for
proper operation. Also, the frequency of the SYNC
signal must meet the following two criteria:
1. SYNC may not toggle outside the frequency range of
200kHz to 2MHz unless it is stopped low to enable the
free-running oscillator.
2. The SYNC frequency can always be higher than the
free-running oscillator frequency, f
OSC
, but should not
be less than 25% below f
OSC
(f
OSC
is set by R
T
).
LTM8045
14
8045fc
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Soft-Start
The LTM8045 soft-start function controls the slew rate
of the power supply output voltage during start-up. A
controlled output voltage ramp minimizes output voltage
overshoot, reduces inrush current from the V
IN
supply,
and facilitates supply sequencing. A capacitor connected
from the SS pin to GND programs the slew rate. In the
event of a commanded shutdown or lockout (RUN pin),
internal undervoltage lockout or a thermal shutdown, the
soft-start capacitor is automatically discharged before
charging resumes, thus assuring that the soft-start occurs
when the LTM8045 restarts. The soft-start time is given
by the equation:
t
SS
= C
SS
/5.45,
where C
SS
is in µF and t
SS
is in seconds.
Configurable Undervoltage Lockout
Figure 1 shows how to configure an undervoltage lock
-
out (UVLO) for the LTM8045. Typically, UVLO is used in
situations where the input supply is current-limited, has
a relatively high source resistance, or ramps up/down
slowly. A switching regulator draws constant power from
the source, so source current increases as source voltage
drops. This looks like a negative resistance load to the
source and can cause the source to current-limit or latch
low under low source voltage
conditions. UVLO prevents
the
regulator from operating at source voltages where
these problems might occur.
The RUN pin has a voltage hysteresis with typical thresh
-
olds of 1.32
V (rising) and 1.29V (falling) and an internal
circuit that draws typically 11.6µA at the RUN threshold.
This makes R
UVLO2
optional, allowing UVLO implemen-
tation with a single resistor. Resistor R
UVLO2
is optional.
R
UVLO2
can be included to reduce the overall UVLO voltage
variation caused by variations in the RUN pin current (see
the Electrical Characteristics section). A good choice for
R
UVLO2
is ≤10k ±1%. After choosing a value for R
UVLO2
,
R
UVLO1
can be determined from either of the following:
R
UVLO1
=
V
IN(RISING)
1.32V
1.32V
R
UVLO2
+ 11.6µA
or
R
UVLO1
=
V
IN(FALLING)
1.29V
1.29V
R
UVLO2
+ 11.6µA
where V
IN(RISING)
and V
IN(FALLING)
are the V
IN
threshold
voltages when rising or falling, respectively.
For example, to disable the LTM8045 for V
IN
voltages
below 3.5V using the single resistor configuration, choose:
R
UVLO1
=
1.29V
+ 11.6µA
= 191k
To activate the LTM8045 for V
IN
voltage greater than 4.5V
using the two resistor configuration, choose R
UVLO2
=
10k and:
R
UVLO1
=
4.5V
1.32V
1.32V
10k
+ 11.6µA
= 22.1k
Internal Undervoltage Lockout
The LTM8045 monitors the V
IN
supply voltage in case V
IN
drops below a minimum operating level (typically about
2.3V). When V
IN
is detected low, the power switch is
deactivated, and while sufficient V
IN
voltage persists, the
soft-start capacitor is discharged. After V
IN
is detected high,
the LTM8045 will reactivate and the soft-start capacitor
will begin charging.
LTM8045
GND
V
IN
RUN
R
UVLO1
R
UVLO2
V
IN
8045 F01
Figure 1. The RUN Pin May Be Used
to Implement an Accurate UVLO
LTM8045
15
8045fc
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Thermal Shutdown
If the part is too hot, the LTM8045 engages its thermal
shutdown, terminates switching and discharges the soft-
start capacitor. When the part has cooled, the part automati
-
cally restarts.
This thermal shutdown is set to engage at
temperatures above the 125°C absolute maximum internal
operating rating to ensure that it does not interfere with
functionality in the specified operating range. This means
that internal temperatures will exceed the 125°C absolute
maximum rating when the overtemperature protection is
active, possibly impairing the device’s reliability.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8045. The LTM8045 is neverthe
-
less a
switching power supply, and care must be taken to
minimize
EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 2
for the suggested layout of the inverting topology applica
-
tion and
Figure 3 for the suggested layout of the SEPIC
topology
application. Ensure that the grounding and heat
sinking are acceptable.
A few rules to keep in mind are:
1. Place the R
FB
and R
T
resistors as close as possible to
their respective pins.
2. Place the C
IN
capacitor as close as possible to the V
IN
and GND connection of the LTM8045.
3. Place the Cout capacitor as close as possible to the
V
OUT
+
and V
OUT
connections of the LTM8045.
4. Place the C
IN
and C
OUT
capacitors such that their
ground currents flow directly adjacent or underneath
the LTM8045.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8045.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figures 2 and 3. The LTM8045 can
benefit from the heat sinking afforded by vias that con
-
nect to internal GND planes at these locations, due to
their
proximity to internal power handling components.
The optimum number of thermal vias depends upon
the printed circuit board design
. For example, a board
might use very small via holes. It should employ more
thermal vias than a board that uses larger holes.
Figure 2. Layout Showing Suggested External
Components, GND Plane and Thermal Vias for
the Inverting Topology Application
8045 F02
GROUND, THERMAL VIAS
V
IN
C
IN
R
T
R
FB
V
OUT
GND
GND
FB RUN
RT
GND
C
OUT
Figure 3. Layout Showing Suggested External
Components, GND Plane and Thermal Vias
for the SEPIC Topology Application
8045 F03
GROUND, THERMAL VIAS
V
IN
C
IN
R
T
R
FB
V
OUT
+
GND
GND
C
OUT
FB RUN
RT

LTM8045EY#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Inverting or SEPIC Module DC/DC Converter with Up to 700mA Output Current
Lifecycle:
New from this manufacturer.
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