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74AUP1G80GW,125

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
74AUP1G80 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 28 June 2012 9 of 22
NXP Semiconductors
74AUP1G80
Low-power D-type flip-flop; positive-edge trigger
C
L
= 15 pF
t
pd
propagation
delay
CP to Q; see Figure 8
[2]
V
CC
= 0.8 V - 28.2 - - - - - ns
V
CC
= 1.1 V to 1.3 V 3.0 7.6 16.7 3.4 18.6 3.4 20.5 ns
V
CC
= 1.4 V to 1.6 V 3.0 5.3 9.8 2.6 11.5 2.6 12.7 ns
V
CC
= 1.65 V to 1.95 V 2.6 4.4 7.6 2.3 9.1 2.3 10.0 ns
V
CC
= 2.3 V to 2.7 V 2.2 3.5 5.7 2.0 6.9 2.0 7.6 ns
V
CC
= 3.0 V to 3.6 V 1.9 3.1 5.0 1.8 5.5 1.8 6.1 ns
f
max
maximum
frequency
CP; see Figure 9
V
CC
= 0.8 V - 50 - - - - - MHz
V
CC
= 1.1 V to 1.3 V - 181 - 120 - 120 - MHz
V
CC
= 1.4 V to 1.6 V - 301 - 190 - 160 - MHz
V
CC
= 1.65 V to 1.95 V - 407 - 240 - 190 - MHz
V
CC
= 2.3 V to 2.7 V - 422 - 300 - 270 - MHz
V
CC
= 3.0 V to 3.6 V - 481 - 320 - 300 - MHz
C
L
= 30 pF
t
pd
propagation
delay
CP to Q; see Figure 8
[2]
V
CC
= 0.8 V - 38.8 - - - - - ns
V
CC
= 1.1 V to 1.3 V 4.9 9.8 20.7 4.4 24.7 4.4 27.2 ns
V
CC
= 1.4 V to 1.6 V 4.0 6.8 12.7 3.5 15.0 3.5 16.5 ns
V
CC
= 1.65 V to 1.95 V 3.5 5.6 9.9 2.2 11.9 2.2 13.0 ns
V
CC
= 2.3 V to 2.7 V 3.1 4.5 7.5 2.8 9.3 2.8 10.2 ns
V
CC
= 3.0 V to 3.6 V 2.9 4.1 6.4 2.7 7.5 2.7 8.3 ns
f
max
maximum
frequency
CP; see Figure 9
V
CC
= 0.8 V - 28 - - - - - MHz
V
CC
= 1.1 V to 1.3 V - 128 - 70 - 70 - MHz
V
CC
= 1.4 V to 1.6 V - 206 - 120 - 110 - MHz
V
CC
= 1.65 V to 1.95 V - 262 - 150 - 120 - MHz
V
CC
= 2.3 V to 2.7 V - 269 - 190 - 170 - MHz
V
CC
= 3.0 V to 3.6 V - 309 - 200 - 190 - MHz
C
L
= 5 pF, 10 pF, 15 pF and 30 pF
t
su(H)
set-up time
HIGH
D to CP; see Figure 9
V
CC
= 0.8 V - 2.5 - - - - - ns
V
CC
= 1.1 V to 1.3 V - 0.5 - 2.2 - 2.2 - ns
V
CC
= 1.4 V to 1.6 V - 0.3 - 1.1 - 1.1 - ns
V
CC
= 1.65 V to 1.95 V - 0.3 - 0.8 - 0.8 - ns
V
CC
= 2.3 V to 2.7 V - 0.2 - 0.6 - 0.6 - ns
V
CC
= 3.0 V to 3.6 V - 0.2 - 0.4 - 0.4 - ns
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 10
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ
[1]
Max Min
(85 C)
Max
(85 C)
Min
(125 C)
Max
(125 C)
74AUP1G80 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 28 June 2012 10 of 22
NXP Semiconductors
74AUP1G80
Low-power D-type flip-flop; positive-edge trigger
[1] All typical values are measured at nominal V
CC
.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
t
su(L)
set-up time
LOW
D to CP; see Figure 9
V
CC
= 0.8 V - 1.7 - - - - - ns
V
CC
= 1.1 V to 1.3 V - 0.3 - 2.0 - 2.0 - ns
V
CC
= 1.4 V to 1.6 V - 0.2 - 1.3 - 1.3 - ns
V
CC
= 1.65 V to 1.95 V - 0.2 - 1.1 - 1.1 - ns
V
CC
= 2.3 V to 2.7 V - 0.3 - 0.8 - 0.8 - ns
V
CC
= 3.0 V to 3.6 V - 0.3 - 0.7 - 0.7 - ns
t
h
hold time D to CP; see Figure 9
V
CC
= 0.8 V - -2.1 - - - - - ns
V
CC
= 1.1 V to 1.3 V - -0.4 - 0.2 - 0.2 - ns
V
CC
= 1.4 V to 1.6 V - -0.3 - 0.1 - 0.1 - ns
V
CC
= 1.65 V to 1.95 V - -0.2 - 0 - 0 - ns
V
CC
= 2.3 V to 2.7 V - -0.2 - 0 - 0 - ns
V
CC
= 3.0 V to 3.6 V - -0.3 - 0 - 0 - ns
t
W
pulse width CP HIGH or LOW;
see Figure 9
V
CC
= 0.8 V - 5.2 - - - - - ns
V
CC
= 1.1 V to 1.3 V - 1.0 - 3.0 - 3.0 - ns
V
CC
= 1.4 V to 1.6 V - 0.8 - 2.0 - 2.0 - ns
V
CC
= 1.65 V to 1.95 V - 0.6 - 2.0 - 2.0 - ns
V
CC
= 2.3 V to 2.7 V - 0.5 - 2.0 - 2.0 - ns
V
CC
= 3.0 V to 3.6 V - 0.5 - 2.0 - 2.0 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz;
V
I
=GNDtoV
CC
[3]
V
CC
= 0.8 V - 1.8 - - - - - pF
V
CC
= 1.1 V to 1.3 V - 1.8 - - - - - pF
V
CC
= 1.4 V to 1.6 V - 1.9 - - - - - pF
V
CC
= 1.65 V to 1.95 V - 2.0 - - - - - pF
V
CC
= 2.3 V to 2.7 V - 2.4 - - - - - pF
V
CC
= 3.0 V to 3.6 V - 2.9 - - - - - pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 10
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ
[1]
Max Min
(85 C)
Max
(85 C)
Min
(125 C)
Max
(125 C)
74AUP1G80 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 28 June 2012 11 of 22
NXP Semiconductors
74AUP1G80
Low-power D-type flip-flop; positive-edge trigger
12. Waveforms
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage drop that occur with the output load.
Fig 8. The clock input (CP) to output (Q) propagation delays
mna652
CP input
Q output
t
PLH
t
PHL
V
M
V
M
V
OH
V
I
GND
D input
V
I
GND
V
OL
V
M
V
M
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage drop that occur with the output load.
Fig 9. The clock input (CP) to output (Q) propagation delays, clock pulse width, D to CP set-up and hold times
and the maximum input clock frequency
mna653
t
h
t
su(L)
t
h
t
PLH
t
W
t
PHL
t
su(H)
1/f
max
V
M
V
M
V
M
V
I
GND
V
I
GND
CP input
D input
V
OH
V
OL
Q output
Table 9. Measurement points
Supply voltage Output Input
V
CC
V
M
V
M
V
I
t
r
= t
f
0.8 V to 3.6 V 0.5 V
CC
0.5 V
CC
V
CC
3.0 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

74AUP1G80GW,125

Mfr. #:
Buy 74AUP1G80GW,125
Manufacturer:
Nexperia
Description:
Flip Flops 1.8V 1G LP D-TYPE + TRIGGER
Lifecycle:
New from this manufacturer.
Delivery:
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