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Run Enable
The RUN pin has an enable threshold of 1.40V maximum,
typically 1.25V with 150mV of hysteresis. It controls the
turn-on of the µModule. The RUN pin can be pulled up to
V
IN
for 5V operation, or a 5V Zener diode can be placed
on the pin and a 10k to 100k resistor can be placed up to
higher than 5V input for enabling the µModule. The RUN
pin can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tied together and
controlled from a single control. See the Typical Applica
-
tion circuits in Figures 20 and 21. The RUN pin can also
be left floating. The RUN pin has a 1µA pull-up current
source that increases to 4.5µA during ramp-up.
Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is provided
in the LTM4648 to sense low output voltages accurately
at the remote load points. This is especially true for high
current loads. It is very important that the DIFFP and
DIFFN are connected properly at the output, and DIFFOUT
is connected to V
OUT_LCL
. Review the parallel schematics
in Figures 20 and 21.
SW Pins
The SW pin is generally for testing purposes by monitor
-
ing the pin. The SW pin can also be used to dampen out
switch node ringing caused by LC parasitic in the switched
current path.
Usually a series R-C combination is used
called a snubber circuit. The resistor will dampen the
resonance and the capacitor is chosen to only affect the
high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usually easier to predict. It combines the power path board
inductance in combination with the MOSFET interconnect
bond wire inductance.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre
-
quency can be measured for its value. The impedance Z
can be calculated
:
Z
L
= 2π f L
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by:
Z
C
=
1
2π f C
These values are a good place to start with. Modification
to these components should be made to attenuate the
ringing with the least amount the power loss.
Temperature Monitoring
Measuring the absolute temperature of a diode is pos
-
sible due to the relationship between current, voltage
and temperature described by the classic diode equation
:
I
D
= I
S
e
V
D
η V
T
or
V
D
= η V
T
ln
I
D
I
S
where I
D
is the diode current, V
D
is the diode voltage, η is
the ideality factor (typically close to 1.0) and I
S
(satura-
tion current) is a process dependent parameter. V
T
can
be broken out to:
V
T
=
k T
q
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmanns constant. V
T
is
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable
temperature sensors. The I
S
term in the equation above
is the extrapolated current through a diode junction when
the diode has zero volts across the terminals. The I
S
term
varies from process to process, varies with temperature,
and by definition must always be less than I
D
. Combining
all of the constants into one term:
K
D
=
η
k
q
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where K
D
= 8.62
−5
, and knowing ln(I
D
/I
S
) is always posi-
tive because I
D
is always greater than I
S
, leaves us with
the equation that:
V
D
= T(KELVIN) K
D
ln
I
D
I
S
where V
D
appears to increase with temperature. It is com-
mon knowledge that a silicon diode biased with a current
source has an approximately
–2mV/°C temperature rela-
tionship (
Figure 7
), which is at odds with the equation. In
fact, the I
S
term increases with temperature, reducing the
ln(I
D
/I
S
) absolute value yielding an approximately 2mV/°C
composite diode voltage slope.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param
-
eters defined by JESD51-9 and are intended for use with
finite element analysis
(FEA)
software modeling tools that
leverage the outcome of thermal modeling, simulation, and
correlation to hardware evaluation performed on a µModule
package mounted to a hardware test boardalso defined
by JESD51-9 (“Test Boards for Area Array Surface Mount
Package Thermal Measurements”). The motivation for
providing these thermal coefficients in found in JESD51-12
(“Guidelines for Reporting and Using Electronic Package
Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulators thermal performance in their ap
-
plication at various electrical and environmental operating
conditions to compliment any FEA activities.
Without FEA
software, the thermal resistances reported in the Pin Con
-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coef
-
ficients are quoted or paraphrased below:
1
.
θ
JA
: the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo
-
sure. This environment is sometimes referred to as
still air although natural convection causes the air to
move. This value is determined with the part mounted
to a JESD51-9 defined test board, which does not reflect
an actual application or viable operating condition.
4648 F07
TEMPERATURE (°C)
–173 –73 27 127
DIODE VOLTAGE (V)
0.4
0.6
0.8
1.0
V
D
I
D
= 100µA
Figure 7. Diode Voltage, V
D
, vs Temperature T (°C)
for Different Bias Currents
An external diode connected PNP transistor can be pulled
up to V
IN
with a resistor to set the current to 100µA for
using this diode connected transistor as a general tem-
perature monitor by monitoring the diode voltage drop
with temperature
,
or a specific temperature monitor can
be used that injects two currents that are at a 10:1 ratio
for very accurate temperature monitoring. See Figure 22
for an example.
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2. θ
JCbottom
: the thermal resistance from junction to ambi-
ent, is the natural convection junction-to-ambient air
thermal resistance
measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to as
still air although natural convection causes the air to
move. This value is determined with the part mounted
to a JESD51-9 defined test board, which does not reflect
an actual application or viable operating condition.
3. θ
JCtop
: the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
JCbottom
, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θ
JB
: the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resistance
where almost all of the heat flows through the bottom of
the µModule and into the board, and is really the sum of
the θ
JCbottom
and the thermal resistance of the bottom
of the part through the solder joints and through a por-
tion of the board. The board temperature is measured a
specified distance from the package
,
using a two sided,
two layer board. This board is described in JESD51-9.
A graphical representation of the aforementioned ther
-
mal resistances is given in Figure 8; blue resistances are
contained within the μ
Module regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal op
-
erating conditions of a μModule. For example, in normal
board-mounted applications,
never does 100% of the
device’s total power loss (heat) thermally conduct exclu
-
sively through the top or exclusively through bottom of the
µModuleas the standard defines for θ
JCtop
and θ
JCbottom
,
respectively. In practice, power loss is thermally dissipated
in both directions away from the package—granted, in the
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
4648 F08
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients

LTM4648EY#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Low VIN, 10A Step-Down DC/DC Module Regulator
Lifecycle:
New from this manufacturer.
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