Data Sheet: Overview
DS171 (v1.0) March 14, 2017 www.xilinx.com
Product Specification 7
The dynamic reconfiguration port (DRP) gives the system designer easy access to the configuration and status registers of
the MMCM, PLL, and XADC. The DRP behaves like a set of memory-mapped registers, accessing and modifying block-
specific configuration bits as well as status and control registers.
Encryption, Readback, and Partial Reconfiguration
In all 7 series FPGAs (except XA7S6 and XA7S15), the FPGA bitstream, which contains sensitive customer IP, can be
protected with 256-bit AES encryption and HMAC/SHA-256 authentication to prevent unauthorized copying of the design.
The FPGA performs decryption on the fly during configuration using an internally stored 256-bit key. This key can reside in
battery-backed RAM or in nonvolatile eFUSE bits.
Most configuration data can be read back without affecting the system's operation. Typically, configuration is an
all-or-nothing operation, but XA Spartan-7 support partial reconfiguration. This is an extremely powerful and flexible feature
that allows the user to change portions of the FPGA while other portions remain static. Users can time-slice these portions
to fit more IP into smaller devices, saving cost and power. Where applicable in certain designs, partial reconfiguration can
greatly improve the versatility of the FPGA.
XADC (Analog-to-Digital Converter)
Highlights of the XADC architecture include:
• Dual 12-bit 1 MSPS analog-to-digital converters (ADCs)
• Up to 17 flexible and user-configurable analog inputs
• On-chip or external reference option
• On-chip temperature (±4°C max error) and power supply (±1% max error) sensors
• Continuous JTAG access to ADC measurements
All Xilinx 7 series FPGAs (except XA7S6 and XA7S15) integrate a new flexible analog interface called XADC. When
combined with the programmable logic capability of the 7 series FPGAs, the XADC can address a broad range of data
acquisition and monitoring requirements. For more information, go to: http://www.xilinx.com/ams
.
The XADC contains two 12-bit 1 MSPS ADCs with separate track and hold amplifiers, an on-chip analog multiplexer (up to
17 external analog input channels supported), and on-chip thermal and supply sensors. The two ADCs can be configured to
simultaneously sample two external-input analog channels. The track and hold amplifiers support a range of analog input
signal types, including unipolar, bipolar, and differential. The analog inputs can support signal bandwidths of at least 500KHz
at sample rates of 1 MSPS. It is possible to support higher analog bandwidths using external analog multiplexer mode with
the dedicated analog input (see UG480
, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS
Analog-to-Digital Converter User Guide).
The XADC optionally uses an on-chip reference circuit (±1%), thereby eliminating the need for any external active
components for basic on-chip monitoring of temperature and power supply rails. To achieve the full 12-bit performance of the
ADCs, an external 1.25V reference IC is recommended.
If the XADC is not instantiated in a design, then by default it digitizes the output of all on-chip sensors. The most recent
measurement results (together with maximum and minimum readings) are stored in dedicated registers for access at any
time via the JTAG interface. User-defined alarm thresholds can automatically indicate over-temperature events and
unacceptable power supply variation. A user-specified limit (for example, 100°C) can be used to initiate an automatic
powerdown.
XA Spartan-7 FPGA Ordering Information
Table 3 shows the speed and temperature grades available for the XA Spartan-7 FPGAs. Some devices might not be
available in every speed and temperature grade.
