NCP1599
http://onsemi.com
13
of the converter. A higher bandwidth generally corresponds
to faster response times and lower overshoots to load
transients. However, the bandwidth should not be much
higher than 1/10 the switching frequency. The NCP1599
operates with a 1.0 MHz switching frequency, so it is
recommended to choose a crossover frequency between
40 kHz − 100 kHz. The schematic of the NCP1599
compensator is shown in Figure 2. The default design uses
Rc and CC1 to form a lag (Type 2) compensator. The CC2
capacitor can be added to form an additional pole that is
typically used to cancel out the ESR zero of the output
capacitor. Finally, if extra phase margin is needed, the C
FF
capacitor can be added (this does not help at low output
voltages, see below). The strategy taken here for choosing
Rc and CC1 is to set the crossover frequency with Rc, and set
the compensator zero with CC1.
Using the selected target crossover frequency, fc, set Rc to:
R
C
+
2p @ f
C
@ C
out
Gm
EA
@ G
CS
@
V
out
V
FB
W
(eq. 11)
fC = Crossover frequency in Hertz (50kHz − 200kHz is
recommended).
The zero, due to the compensation capacitor (Cc1) and the
compensation resistor (Rc), is located at:
f
Z1
+
1
2p C
C1
R
C
(eq. 12)
When fast transient responses are desired, fZ1 should be
placed as high as possible, however it should not be higher
than the selected crossover frequency fc. The guideline
proposed here is to choose CC1 such that fZ1 falls somewhere
between the power pole fP1 and 1⁄2 decade before the
selected crossover frequency fc:
3.16
2p R
C
f
C
v C
C1
v
1
2p f
p1
R
C
(eq. 13)
The compensation capacitor (Cc1) and the output resistor
of error amplifier RGM creates another pole of the system,
and it’s located at:
f
p2
+
1
2p C
C1
R
GM
,
(eq. 14)
Where R
GM
= 66 • 10
3
W.
In this compensation scheme, the pole created by CC2 is
used to cancel out the zero created by the ESR of the output
capacitor. This pole is located at:
f
p3
+
1
2p @ C
C2
@
R
C
R
GM
R
C
)R
GM
,
(eq. 15)
For the typical case, use CC2 if:
f
ESR
t
f
S
2
(eq. 16)
C
C2
+
R
GM
) R
C
2p f
ESR
R
GM
R
C
(eq. 17)
A feed−forward capacitor is recommended for most
designs. The large resistor value and the parasitic
capacitance of the FB Pin can cause a high frequency pole
that can reduce the overall system phase margin. By placing
a feed−forward capacitor C
FF
, these effects can be
significantly reduced. C
FF
will provide a positive phase shift
(lead) that can be used to increase phase margin. However,
it is important to note that the effectiveness of C
FF
decreases
with output voltage. This is due to the fact that the frequency
of the zero f
zff
and pole f
pff
get closer together as the output
voltage is reduced.
The frequency of the feed−forward zero and pole are:
f
Zff
+
1
2p R
FB1
C
ff
(eq. 18)
f
pff
+
1
2p R
FB1
C
ff
R
FB1
) R
FB2
R
FB2
+ f
Zff
V
out
V
FB
(eq. 19)
Power Dissipation
The NCP1599 is available in thermally enhanced 6−pin,
DFN package. When the die temperature reaches +185°C,
the NCP1599 shuts down (see the Thermal−Overload
Protection section). The power dissipated in the device is the
sum of the power dissipated from supply current (PQ),
power dissipated due to switching the internal power
MOSFET (P
SW
), and the power dissipated due to the RMS
current through the internal power MOSFET (PON). The
total power dissipated in the package must be limited so the
junction temperature does not exceed its absolute maximum
rating of +150°C at maximum ambient temperature.
Calculate the power lost in the NCP1599 using the following
equations:
1. High side MOSFET
The conduction loss in the top switch is:
P
HSON
+ I
2
RMS_HSFET
R
DS(on)HS
(eq. 20)
Where:
I
RMS_FET
+
ǒ
I
out
2
)
DI
PP
2
12
Ǔ
D
Ǹ
(eq. 21)
DI
PP
is the peak−to−peak inductor current ripple.
The power lost due to switching the internal power high side
MOSFET is:
P
HSSW
+
V
in
@ I
out
@
ǒ
t
r
) t
f
Ǔ
@ f
SW
2
(eq. 22)
t
r
and t
f
are the rise and fall times of the internal power
MOSFET measured at SW node.
