Data Sheet ADuM3480/ADuM3481/ADuM3482
Rev. A | Page 17 of 20
APPLICATIONS INFORMATION
SUPPLY VOLTAGES
The ADuM3480/ADuM3481/ADuM3482 devices are built
around a fixed voltage internal data transfer core. The core
voltage is 2.7 V, which is generated by regulating the V
DD1
and
V
DD2
voltages with an internal LDO. To ensure proper headroom
for the LDO, the V
DD1
and V
DD2
inputs must be in the 3.0 V to 5.5 V
range. Additional pins, V
DDC1
and V
DDC2
, are provided for direct
bypass of the LDO output, ensuring clean stable core operation.
Bypass capacitors to ground of between 0.01 μF and 0.1 μF are
required for each of these supply or dedicated bypass pins.
The ADuM3480/ADuM3481/ADuM3482 provide independent
supplies for the I/O buffers, V
DDL1
and V
DDL2
, which have wider
operating ranges than that required for the core. This allows the
I/O supply voltage to range between 1.8 V and 5.5 V. The V
DDLx
supplies must also be bypassed with between 0.01 μF and 0.1 μF
capacitors.
Having independent power supplies for the I/O and core allows
several power configurations depending on the I/O voltage
required and the available power supply rails. If one power
supply is available, the V
DDx
and V
DDLx
pins can be connected
together and operate between 3.0 V and 5.5 V. If lower I/O
supply voltage is required, to interface with low voltage logic,
two supply rails are required. For example, if the I/O is 1.8 V
logic, the V
DDLx
pin can be connected to a 1.8 V supply rail. The
core supply voltage for V
DDx
requires an input of between 3.0 V and
5.5 V, so an available 3.3 V or 5 V supply rail can be used. The I/O
and core supply voltage on each side are independent and different
configurations can be used on each side of the device.
PRINTED CIRCUIT BOARD LAYOUT
The ADuM3480/ADuM3481/ADuM3482 digital isolator requires
no external interface circuitry for the logic interfaces. Power supply
bypassing to the local ground is required at all four power supply
pins, V
DD1
, V
DDL1
, V
DD2
, and V
DDL2
, as well as at the two internal
regulator bypass pins: V
DDC1
and V
DDC2
(see Figure 15). Placement
of the recommended bypass capacitors is shown in Figure 15. The
capacitor value should be between 0.01 μF and 0.1 μF. The total lead
length between both ends of the capacitor and the input power
supply pin should not exceed 20 mm.
V
DDL1
GND
1
V
IA
V
IB
V
IC
/V
OC
V
ID
/V
OD
CTRL
1
V
DD1
V
DDC1
GND
1
V
DDL2
GND
2
V
OA
V
OB
V
OC
/V
IC
V
OD
/V
ID
CTRL
2
V
DD2
V
DDC2
GND
2
10459-016
Figure 15. Recommended Printed Circuit Board (PCB) Layout
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, design the board layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to follow this design guideline can allow voltage differentials
between pins that exceed the absolute maximum ratings of the
device during high voltage transients, which can lead to latch-up or
permanent damage.
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high to low transition may
differ from the propagation delay time of a low to high transition.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
10459-017
Figure 16. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Channel to channel matching refers to the maximum amount of
time that the propagation delay differs between channels within
a single ADuM3480/ADuM3481/ADuM3482 component.
Propagation delay skew refers to the maximum amount of time
that the propagation delay differs between multiple ADuM3480/
ADuM3481/ADuM3482 components operating under the same
conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the decoder.
The decoder is bistable and is, therefore, either set or reset by
the pulses indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1.7 μs, the current
dc state is sent to the output to ensure dc correctness at the output.
If the decoder receives no pulses for more than about 5 μs, the
input side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 17,
Table 18, or Table 19) by the watchdog timer circuit.
