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LTC2606IDD#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC2606/LTC2616/LTC2626
13
26061626fb
OPERATION
Power-On Reset
The LTC2606/LTC2616/LTC2626 clear the outputs to
zero-scale when power is fi rst applied, making system
initialization consistent and repeatable. The LTC2606-1/
LTC2616-1/LTC2626-1 set the voltage outputs to mid-scale
when power is fi rst applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2606/
LTC2616/LTC2626 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.3V ≤ V
REF
≤ V
CC
+ 0.3V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin 9) is in transition.
Transfer Function
The digital-to-analog transfer function is:
V
OUT(IDEAL)
=
k
2
N
⎛
⎝
⎜
⎞
⎠
⎟
V
REF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V
REF
is the voltage at REF
(Pin 6).
Serial Digital Interface
The LTC2606/LTC2616/LTC2626 communicate with a
host using the standard 2-wire I
2
C interface. The Timing
Diagrams (Figures 1 and 2) show the timing relationship
of the signals on the bus. The two bus lines, SDA and
SCL, must be high when the bus is not in use. External
pull-up resistors or current sources are required on these
lines. The value of these pull-up resistors is dependent
on the power supply and can be obtained from the I
2
C
specifi cations. For an I
2
C bus operating in the fast mode,
an active pull-up will be necessary if the bus capacitance is
greater than 200pF. The V
CC
power should not be removed
from the LTC2606/LTC2616/LTC2626 when the I
2
C bus
is active to avoid loading the I
2
C bus lines through the
internal ESD protection diodes.
The LTC2606/LTC2616/LTC2626 are receive-only (slave)
devices. The master can write to the LTC2606/LTC2616/
LTC2626. The LTC2606/LTC2616/LTC2626 do not respond
to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has fi nished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I
2
C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the lat-
est byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge clock
pulse. The slave-receiver must pull down the SDA bus line
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse.
The LTC2606/LTC2616/LTC2626 respond to a write by a
master in this manner. The LTC2606/LTC2616/LTC2626
do not acknowledge a read (retains SDA HIGH during the
period of the Acknowledge clock pulse).
LTC2606/LTC2616/LTC2626
14
26061626fb
OPERATION
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: V
CC
, GND or fl oat. This results
in 27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
Table 1. Slave Address Map
CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0
GND GND GND 0 0 1 0 0 0 0
GND GND FLOAT 0 0 1 0 0 0 1
GND GND V
CC
0010010
GND FLOAT GND 0 0 1 0 0 1 1
GND FLOAT FLOAT 0 1 0 0 0 0 0
GND FLOAT V
CC
0100001
GND V
CC
GND 0 1 0 0 0 1 0
GND V
CC
FLOAT 0 1 0 0 0 1 1
GND V
CC
V
CC
0110000
FLOAT GND GND 0 1 1 0 0 0 1
FLOAT GND FLOAT 0 1 1 0 0 1 0
FLOAT GND V
CC
0110011
FLOAT FLOAT GND 1 0 0 0 0 0 0
FLOAT FLOAT FLOAT 1 0 0 0 0 0 1
FLOAT FLOAT V
CC
1000010
FLOAT V
CC
GND 1 0 0 0 0 1 1
FLOAT V
CC
FLOAT 1 0 1 0 0 0 0
FLOAT V
CC
V
CC
1010001
V
CC
GND GND 1 0 1 0 0 1 0
V
CC
GND FLOAT 1 0 1 0 0 1 1
V
CC
GND V
CC
1100000
V
CC
FLOAT GND 1 1 0 0 0 0 1
V
CC
FLOAT FLOAT 1 1 0 0 0 1 0
V
CC
FLOAT V
CC
1100011
V
CC
V
CC
GND 1 1 1 0 0 0 0
V
CC
V
CC
FLOAT 1 1 1 0 0 0 1
V
CC
V
CC
V
CC
1110010
GLOBAL ADDRESS 1 1 1 0 0 1 1
In addition to the address selected by the address pins,
the parts also respond to a global address. This address
allows a common write to all LTC2606, LTC2616 and
LTC2626 parts to be accomplished with one 3-byte write
transaction on the I
2
C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven during
address detection to determine if they are fl oating.
Write Word Protocol
The master initiates communication with the LTC2606/
LTC2616/LTC2626 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2606/
LTC2616/LTC2626 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the
global address. The master then transmits three bytes of
data. The LTC2606/LTC2616/LTC2626 acknowledges each
byte of data by pulling the SDA line low at the 9th clock of
each data byte transmission. After receiving three complete
bytes of data, the LTC2606/LTC2616/LTC2626 executes the
command specifi ed in the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2606/LTC2616/LTC2626 do not
acknowledge the extra bytes of data (SDA is high during
the 9th clock).
The format of the three data bytes is shown in Figure 3.
The fi rst byte of the input word consists of the 4-bit com-
mand and four don’t care bits. The next two bytes consist
of the 16-bit data word. The 16-bit data word consists of
the 16-, 14- or 12-bit input code, MSB to LSB, followed by
0, 2 or 4 don’t care bits (LTC2606, LTC2616 and LTC2626
respectively).
A typical LTC2606 write transaction is shown
in Figure 4.
The command assignments (C3-C0) are shown in Table 2.
The fi rst four commands in the table consist of write and
update operations. A write operation loads a 16-bit data
word from the 32-bit shift register into the input register.
In an update operation, the data word is copied from the
input register to the DAC register and converted to an
analog voltage at the DAC output. The update operation
also powers up the DAC if it had been in power-down
mode. The data path and registers are shown in the Block
Diagram.
LTC2606/LTC2616/LTC2626
15
26061626fb
OPERATION
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DAC output is not needed. When in power-down, the buffer
amplifi er, bias circuit and reference input is disabled and
draws essentially zero current. The DAC output is put into a
high impedance state, and the output pin is passively pulled
to ground through 90k resistors. Input- and DAC-register
contents are not disturbed during power-down.
Table 2
COMMAND*
C3 C2 C1 C0
0 0 0 0 Write to Input Register
0 0 0 1 Update (Power Up) DAC Register
0 0 1 1 Write to and Update (Power Up)
0 1 0 0 Power Down
1 1 1 1 No Operation
*Command codes not shown are reserved and should not be used.
The DAC channel can be put into power-down mode by
using command 0100
b
. The 16-bit data word is ignored.
The supply and reference currents are reduced to almost
zero when the DAC is powered down; the effective resis-
tance at REF becomes a high impedance input (typically
>1GΩ).
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 2 or
performing an asychronous update (LDAC) as described
in the next section. The DAC is powered up as its voltage
output is updated. When the DAC in powered-down state
is powered up and updated, normal settling is delayed. The
main bias generation circuit block has been automatically
shut down in addition to the DAC amplifi er and reference
input and so the power-up delay time is:
12μs (for V
CC
= 5V) or 30μs (for V
CC
= 3V)
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 2,
the LDAC pin asynchronously updates the DAC register
with the contents of the input register. Asynchronous
update is disabled when the input word is being clocked
into the part.
If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC register to be updated
with the contents of the input register.
If the input word is being written to the part, a low going
pulse on the LDAC pin before the completion of three bytes
of data powers up the DAC but does not cause the output
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recognized,
the command specifi ed in the 24-bit word just transferred
is executed and the DAC output is updated.
Figure 3
C3
1ST DATA BYTE
Input Word (LTC2606)
Write Word Protocol for LTC2606/LTC2616/LTC1626
C2
C1
C0
X
X
X
X
D13D14D15
S
WA
SLAVE ADDRESS
1ST DATA BYTE
D12
D11 D10 D9 D8
D7
D6
D5 D4 D3 D2 D1
D0
A 2ND DATA BYTE A 3RD DATA BYTE A P
2606 F03
2ND DATA BYTE
INPUT WORD
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2616)
C2
C1
C0
X
X
X
X
D11D12D13
D10
D9 D8 D7 D6
D5
D4
D3 D2 D1 D0 X
X
2ND DATA BYTE 3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2626)
C2
C1
C0
X
X
X
X
D9D10D11
D8
D7 D6 D5 D4
D3
D2
D1 D0 X X X
X
2ND DATA BYTE 3RD DATA BYTE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTC2606IDD#PBF

Mfr. #:
Buy LTC2606IDD#PBF
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 16-B R2R DACs w/ I2C Int
Lifecycle:
New from this manufacturer.
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