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AD7888ARU-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
–3–
AD7888
Parameter A Version
1
B Version
1
Unit Test Condition/Comment
POWER REQUIREMENTS
V
DD
2.7/5.25 2.7/5.25 V min/max
I
DD
Normal Mode
5
(Static) 700 700 µA max
Normal Mode
(Operational) 700 700 µA typ f
SAMPLE
= 125 kSPS
Using Standby Mode 450 450 µA typ f
SAMPLE
= 50 kSPS
Using Shutdown Mode 80 80 µA typ f
SAMPLE
= 10 kSPS
12 12 µA typ f
SAMPLE
= 1 kSPS
Standby Mode
6
µA max V
DD
= 2.7 V to 5.25 V
Shutdown Mode
6
22 µA max V
DD
= 4.75 V to 5.25 V (0.5 µA typ)
11 µA max V
DD
= 2.7 V to 3.6 V
Normal-Mode Power Dissipation 3.5 3.5 mW max V
DD
= 5 V
2.1 2.1 mW max V
DD
= 3 V
Shutdown Power Dissipation 10 10 µW max V
DD
= 5 V
33 µW max V
DD
= 3 V
Standby Power Dissipation 1 1 mW max V
DD
= 5 V
600 600 µW max V
DD
= 3 V
NOTES
1
Temperature ranges as follows: A Version: –40°C to +105°C; B Version: –40°C to +105°C.
2
See Terminology.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ 25°C to ensure compliance.
5
All digital inputs @ GND except CS @ V
DD
. No load on the digital outputs. Analog inputs @ GND.
6
SCLK @ GND when SCLK off. All digital inputs @ GND except for CS @ V
DD
. No load on the digital outputs. Analog inputs @ GND.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to AGND . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to AGND . . . . –0.3 V to V
DD
+ 0.3 V
REFIN/REFOUT to AGND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . . ± 10 mA
Operating Temperature Range
Commercial
(A Version) . . . . . . . . . . . . . . . . . . . . . . –40°C to +105°C
(B Version) . . . . . . . . . . . . . . . . . . . . . . °C to +105°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC, TSSOP Package, Power Dissipation . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . 124.9°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W (TSSOP)
θ
JC
Thermal Impedance . . . . . . . . . . . . . 42.9°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.6°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7888 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
220
220
−40
AD7888
–4–
Limit at T
MIN
, T
MAX
(A, B Versions)
Parameter 4.75 V to 5.25 V 2.7 V to 3.6 V Unit Description
f
SCLK
2
2 2 MHz max
t
CONVERT
14.5 t
SCLK
14.5 t
SCLK
t
ACQ
1.5 t
SCLK
1.5 t
SCLK
Throughput Time = t
CONVERT
+ t
ACQ
= 16 t
SCLK
t
1
10 10 ns min CS to SCLK Setup Time
t
2
3
30 60 ns max Delay from CS until DOUT 3-State Disabled
t
3
3
75 100 ns max Data Access Time after SCLK Falling Edge
t
4
20 20 ns min Data Setup Time Prior to SCLK Rising Edge
t
5
20 20 ns min Data Valid to SCLK Hold Time
t
6
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK High Pulsewidth
t
7
0.4 t
SCLK
0.4 t
SCLK
ns min SCLK Low Pulsewidth
t
8
4
80 80 ns max CS Rising Edge to DOUT High Impedance
t
9
55µs typ Power-Up Time from Shutdown
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V ± 10% and time for an output to
cross 0.4 V or 2.0 V with V
DD
= 3 V ± 10%.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(T
A
= T
MIN
to T
MAX
, unless otherwise noted)
1.6V
I
OL
200␮A
200␮A
I
OH
TO
OUTPUT
PIN
C
L
50pF
Figure 1. Load Circuit for Digital Output Timing Specifications
REV. C
AD7888
–5–
PIN CONFIGURATIONS
SOIC AND TSSOP
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
CS
REF IN/REF OUT
V
DD
AGND
AIN1
AIN2
AIN3
AIN4
SCLK
DOUT
DIN
AGND
AIN8
AIN7
AIN6
AIN5
AD7888
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Function
1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7888 and also frames the serial data transfer.
2 REF IN/REF OUT Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7888.
Alternatively, the internal reference can be disabled and an external reference applied to this input.
The voltage range for the external reference is from 1.2 V to V
DD
.
3V
DD
Power Supply Input. The V
DD
range for the AD7888 is from 2.7 V to 5.25 V.
4, 13 AGND Analog Ground. Ground reference point for all circuitry on the AD7888. All analog input signals and
any external reference signals should be referred to this AGND voltage. Both of these pins should
connect to the AGND plane of a system.
5–12 AIN1–AIN8 Analog Input 1 through Analog Input 8. Eight single-ended analog input channels that are multiplexed
into the on-chip track/hold. The analog input channel to be converted is selected by using the ADD0
through ADD2 bits of the Control Register. The input range for all input channels is 0 to V
REF
. Any
unused input channels should be connected to AGND to avoid noise pickup.
14 DIN Data In. Logic Input. Data to be written to the AD7888’s Control Register is provided on this input
and is clocked into the register on the rising edge of SCLK (see Control Register section).
15 DOUT Data Out. Logic Output. The conversion result from the AD7888 is provided on this output as a serial
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists
of four leading zeros followed by the 12 bits of conversion data, which is provided MSB first.
16 SCLK Serial Clock. Logic Input. SCLK provides the serial clock for accessing data from the part and writing
serial data to the Control Register. This clock input is also used as the clock source for the AD7888’s
conversion process.
REV. C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

AD7888ARU-REEL

Mfr. #:
Buy AD7888ARU-REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2.7V-5.25V Micropwr 8-Ch 125kSPS 12-Bit
Lifecycle:
New from this manufacturer.
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