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Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0269EN
AV02-0131EN - October 29, 2007
Figure 18. LC coupling network.
Table 1. Typical component values for LC coupling network.
Although the series coupling impedance is minimized to re-
duce insertion loss, it has to be suciently large to limit the
peak current to the desired level in the worst expected pow-
erline load condition. The peak output current is eectively
limited by the total series coupling resistance, which is made
up of the series resistance of L1 & L2, the series resistance of
the fuse and any other resistive elements connected in the
coupling network.
Line Driver
The dual line drivers combined is capable of driving power-
line load impedances with output signals up to 7 VPP. The
biasing point of the line driver is controlled internally. The
biasing point set enables optimum modulation frequencies
up to 150 kHz.
The outputs of the line drivers are coupled onto the pow-
erline using a simple dierential mode LC coupling circuit
as shown in Figure 18. Refer to Table 1 for some typical
component values. Capacitors C5 & C6 and inductor L3
attenuate the 50/60 Hz powerline transmission frequency.
A suitable value for L3 can range in value from 200 µH to 1
mH. To reduce the series coupling impedance at the modu-
lation frequency, L1 & L2 are included to compensate for the
reactive impedance of C3 & C4. These inductors should be
of a low resistance type capable of meeting the peak cur-
rent requirements. To meet safety regulatory requirements,
capacitors C5 & C6 need to be of X2 safety rated. Since these
types of capacitors typically have a very wide tolerance
range of 20%, it is recommended to use as low a Q factor as
possible for the L1/C3 & L2/C4 combinations.
L
N
330µH
220nF
Type X2
220nF
Type X2
C3
C4
C5
C6
L1
L2
L3
Vout1
Vout2
Carrier Frequency (kHz)
LC Coupling
L1 (or L2) (µH) C3 (or C4) (nF)
110 15 150
120 10 220
132 6.8 220
150 6.8 220
Normal Over-Temperature I
out
< -0.25 A
Status output High Low Low (pulsed)
To reduce power dissipation when not operating in transmit
mode the line driver stage is shut down to a low power high
impedance state (or tri-state) by pulling the Tx-en input (pin
4) to a logic low state.
External Transient Voltage Protection
To protect ACPL-0820 against high voltage transients
caused by voltage surges and disconnecting/connecting
the modem, it is necessary to add external bi-directional
transient voltage protectors such as D1, D2 (both 5V rated)
& D3 (7V rated) as shown in Figure 17 in the circuit. But care
must be taken to ensure that the total output capacitance
as seen by each output is not more than 1nF to prevent
oscillations.
Another mandatory protection against AC power surges
from the mains can be achieved by adding an appropriate
Metal Oxide Varistor (MOV) across the powerline terminals
after the fuse.
Internal Protection and Sensing
ACPL-0820 includes 2 sensing and protection features to
ensure robust operation under wide ranging environmental
conditions.
The 1st protection features is the over-temperature shut-
down. This particular feature protects the line driver stage
from over-temperature stress. Should the IC junction tem-
perature reach a level above 150°C, the line driver circuit will
be shut down and the output of Status (pin 1) is pulled to
the logic low state simultaneously.
The 2nd feature is load detection sensing feature. The pow-
erline impedance is quite unpredictable and varies not just
at dierent connection points but is also time variant. ACPL-
0820 includes this current sensing feature, which may be
utilized to feedback information on the instantaneous pow-
erline load conditions. Should the output current reaches a
level greater than 0.5 App, the status pin output is pulled
to a logic low state for the entire duration when the peak
current is exceeding -0.25 A, as shown in Figure 10. Using
the period of the pulse together with the known coupling
impedance, the actual powerline load can be calculated.
Table 2 shows the logic output of the Status pin.
Table 2. Status pin logic output.
