ICS1562B Application Information
Output Circuit Considerations for the ICS1562B
Output Circuitry
The dot clock signals CLK and CLK- are typically the highest
frequency signals present in the workstation. To minimize
problems with EMI, crosstalk, and capacitive loading extra
care should be taken in laying out this area of the PC board.
The ICS1562B is packaged in a 0.2”-wide 16-pin SOIC pack-
age. This permits the clock generator, crystal, and related
components to be laid out in an area the size of a postage stamp.
The ICS1562B should be placed as close as possible to the
RAMDAC. The CLK and CLK- pins are running at VHF
frequencies; one should minimize the length of PCB trace
connecting them to the RAMDAC so that they don’t become
radiators of RF energy.
At the frequencies that the ICS1562B is capable of, PC board
traces may be long enough to be a significant portion of a
wavelength of that frequency. PC traces for CLK and CLK-
should be treated as transmission lines, not just interconnecting
wires. These lines can take two forms: microstrip and stripline.
A microstrip line is shown below:
Essentially, the microstrip is a copper trace on a PCB over a
ground plane. Typically, the dielectric is G10 glass epoxy. It
differs from a standard PCB trace in that its width is calculated
to have a characteristic impedance. To calculate the charac-
teristic impedance of a microstrip line one must know the width
and thickness of the trace, and the thickness and dielectric
constant of the dielectric. For G10 glass epoxy, the dielectric
constant (e
r
) is about 5. Propagation delay is strictly a function
of dielectric constant. For G10 propagation, delay is calculated
to be 1.77 ns/ft.
Stripline is the other form a PCB transmission line can take. A
buried trace between ground planes (or between a power plane
and a ground plane) is common in multi-layer boards.
Attempting to create a workstation design without the use of
multi-layer boards would be adventurous to say the least, the
issue would more likely be whether to place the interconnect
on the surface or between layers. The between layer approach
would work better from an EMI standpoint, but would be more
difficult to lay out. A stripline is shown below:
Using 1 oz. copper (0.0015” thick) and 0.040” thickness G10,
a 0.010” trace will exhibit a characteristic impedance of 75Ω
in a stripline configuration.
Typically, RAMDACs require a V
ih
of V
AA
-1.0 Volts as a
guaranteed logical “1” and a V
il
of V
AA
-1.6 as a guaranteed
logical “0.” Worst case input capacitance is 10 pF.
Output circuitry for the ICS1562B is shown in the following
diagram. It consists of a 4/1 current mirror, and two open drain
output FETs along with inverting buffers to alternately enable
each current-sinking driver. Both CLK and CLK- outputs are
connected to the respective CLOCK and
CLOCK inputs of the
RAMDAC with transmission lines and terminated in their
equivalent impedances by the Thevenin equivalent impedances
of R1 and R2 or R1’ and R2’.
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