MAX9310A
1:5 Clock Driver with Selectable LVPECL
Inputs/Single-Ended Inputs and LVDS Outputs
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Detailed Description
The MAX9310A is a low-skew 1:5 differential driver with
two selectable LVPECL inputs and LVDS outputs,
designed for clock distribution applications. The select-
ed clock accepts a differential input signal and repro-
duces it on five separate differential LVDS outputs. The
inputs are biased with internal resistors such that the
output is differential low when inputs are open. An on-
chip V
BB
reference output is available for single-ended
input operation. The device is guaranteed to operate at
frequencies up to 1.0GHz with LVDS output levels con-
forming to the EIA/TIA-644 standard.
The MAX9310A is designed for 3V to 3.6V operation in
systems with a nominal 3.3V supply.
Differential LVPECL Input
The MAX9310A has two input differential pairs that
accept differential LVPECL/HSTL inputs, and can be
configured to accept single-ended LVPECL inputs
through the use of the V
BB
voltage-reference output.
Each differential input pair has to be independently ter-
minated. A select pin (CLKSEL) is used to activate the
desired input. The maximum magnitude of the differen-
tial signal applied to the input is 3V. Specifications for
the high and low voltages of a differential input (V
IHD
and V
ILD
) and the differential input voltage (V
IHD
- V
ILD
)
apply simultaneously.
Single-Ended Inputs and V
BB
The differential inputs can be configured to accept a
single-ended input through the use of the V
BB
refer-
ence voltage. A noninverting, single-ended input is pro-
duced by connecting V
BB
to the CLK_ input and
applying a single-ended signal to the CLK_ input.
Similarly, an inverting input is produced by connecting
V
BB
to the CLK_ input and applying the signal to the
CLK_ input. With a differential input configured as sin-
gle ended (using V
BB
), the single-ended input can be
driven to V
CC
and GND, or with a single-ended
LVPECL signal. Note the single-ended input must be at
least V
BB
±95mV or a differential input of at least 95mV
to switch the outputs to the V
OH
and V
OL
levels speci-
fied in the DC Electrical Characteristics table (Figure 1).
When using the V
BB
reference output, bypass it with a
0.01µF ceramic capacitor to V
CC
. If the V
BB
reference
is not used, leave unconnected. The V
BB
reference can
source or sink 500µA. Use V
BB
only for inputs that are
on the same device as the V
BB
reference.
Synchronous Enable
The MAX9310A is synchronously enabled and disabled
with outputs in a differential low state to eliminate short-
ened clock pulses. EN is connected to the input of an
edge-triggered D flip-flop. After power-up, drive EN low
and toggle the selected clock input to enable the out-
puts. The outputs are enabled on the falling edge of the
selected clock input after EN goes low. The outputs are
set to a differential low state on the falling edge of the
selected clock input after EN goes high (Figure 3).
Input Bias Resistors
Internal biasing resistors ensure a (differential) output
low condition in the event that the inputs are not con-
nected. The inverting input (CLK_) is biased with a
75kΩ pulldown to GND and a 75kΩ pullup to V
CC
. The
noninverting input (CLK_) is biased with a 75kΩ pull-
down to GND.
Differential LVDS Output
The LVDS outputs must be terminated with 100Ω
across Q and Q, as shown in the Typical Application
Circuit. The outputs are short-circuit protected.
