MC9S12D-FamilyPP
Rev 6.1, 23-Oct-02
MC9S12D-Family
Product Brief
16-Bit Microcontroller
Designed for automotive multiplexing applications, members of the MC9S12D-Family of 16 bit Flash-
based microcontrollers are fully pin compatible and enable users to choose between different memory
and peripheral options for scalable designs. All MC9S12D-Family members are composed of standard
on-chip peripherals including a 16-bit central processing unit (CPU12), up to 512K bytes of Flash
EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications
interfaces (SCI), three serial peripheral interfaces (SPI), IIC-bus, an enhanced capture timer (ECT), two
8-channel 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM),
J1850 interface and up to five CAN 2.0 A, B software compatible modules (MSCAN12). System
resource mapping, clock generation, interrupt control and bus interfacing are managed by the system
integration module (SIM). The MC9S12D-Family has full 16-bit data paths throughout, however, the
external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for
lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22
I/O ports are available with interrupt capability allowing Wake-Up from STOP or WAIT mode.
Features
NOTE
Not all features listed here are available in all configurations.
Additional information about D and B family inter-operability is given in:
EB386 “HCS12 D-Family Compatibility Considerations” and
EB388 “Using the HCS12 D-Family as a development platform for the HCS12 B family”
• 16-bit CPU12
Upward compatible with M68HC11 instruction set
Interrupt stacking and programmers model identical to M68HC11
HCS12 Instruction queue
Enhanced indexed addressing
Multiplexed bus
Single chip or expanded
16 address/16 data wide or 16 address/8 data narrow modes
External address space 1MByte for Data and Program space (112 pin package only)
Wake-up interrupt inputs depending on the package option
8-bit port H
2-bit port J1:0
2-bit port J7:6 shared with IIC, CAN4 and CAN0 module
8-bit port P shared with PWM or SPI1,2
Memory options
32K, 64K, 128K, 256K, 512K Byte Flash EEPROM
1K, 2K, 4K Byte EEPROM
2K, 4K, 8K, 12K, 14K Byte RAM
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Produ
Go to: www.freescale.com
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MC9S
2 PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02
Analog-to-Digital Converters
One or two 8-channel modules with 10-bit resolution depending on the package option
External conversion trigger capability
Up to five 1M bit per second, CAN 2.0 A, B software compatible modules
Five receive and three transmit buffers
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
Four separate interrupt channels for Receive, Transmit, Error and Wake-up
Low-pass filter wake-up function in STOP mode
Loop-back for self test operation
Enhanced Capture Timer (ECT)
16-bit main counter with 7-bit prescaler
8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer
Input capture filters and buffers, three successive captures on four channels, or two captures on four
channels with a capture/compare selectable on the remaining four
Four 8-bit or two 16-bit pulse accumulators
16-bit modulus down-counter with 4-bit prescaler
Four user-selectable delay counters for signal filtering
8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages)
8-bit, 8-channel or 16-bit, 4-channel
Separate control for each pulse width and duty cycle
Center- or left-aligned outputs
Programmable clock select logic with a wide range of frequencies
Serial interfaces
Two asynchronous serial communications interfaces (SCI)
Up to three synchronous serial peripheral interfaces (SPI)
IIC
SAE J1850 Compatible Module (BDLC)
10.4 kbps Variable Pulse Width format
Byte level receive and transmit
4x receive mode supported
SIM (System Integration Module)
CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset)
MEBI (multiplexed external bus interface)
INT (interrupt control)
Clock generation
Phase-locked loop clock frequency multiplier
Limp home mode in absence of external clock
Clock Monitor
Low power 0.5 to 16 MHz crystal oscillator reference clock
Operating frequency for ambient temperatures T
A
-40°C <= T
A
<= 125°C
50MHz equivalent to 25MHz Bus Speed for single chip
40MHz equivalent to 20MHz Bus Speed in expanded bus modes.
Internal 5V to 2.5V Regulator
112-Pin LQFP or 80-Pin QFP package
I/O lines with 5V input and drive capability
5V A/D converter inputs and 5V I/O
2.5V logic supply
Development support
Single-wire background debug mode (BDM)
On-chip hardware breakpoints
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02 3
Pin out explanations:
A/D is the number of modules/total number of A/D channels.
I/O is the sum of ports capable to act as digital input or output.
112 Pin Packages:
Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16 input
only.
22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ)
80 Pin Packages:
Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 input only.
11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ)
CAN0 pins are shared between J1850 pins.
CAN0 can be routed under software control from PM1:0 to pins PM3:2 or PM5:4 or PJ7:6.
CAN4 pins are shared between IIC pins.
CAN4 can be routed under software control from PJ7:6 to pins PM5:4 or PM7:6.
Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4.
Versions with 3 CANs modules will have CAN0, CAN1 and CAN4.
Versions with 2 CAN modules will have CAN0 and CAN4.
Versions with one CAN module will have CAN0.
Versions with 2 SPI modules will have SPI0 and SPI1.
Versions with 1 SPI will have SPI0.
SPI0 can be routed to either Ports PS7:4 or PM5:2.
SPI2 pins are shared with PWM7:4; In 112 pin versions SPI2 can be routed under software control to
PH7:4. In 80 pin packages SS
-signal of SPI2 is not bonded out!
NOTE
CAN and SPI routing features are not available on the 1st PC9S12DP256 mask set 0K36N!
Table 1 List of MC9S12D-Family members
Flash RAM EEPROM Package Device CAN J1850 SCI SPI IIC A/D PWM I/O
512K 14K 4K 112LQFP
DP512512312/16891
DT512302312/16891
DJ512212312/16891
256K 12K 4K
112LQFP
DT256302312/16891
DJ256212312/16891
DG256202312/16891
80QFP
DJ256212311/8759
DG256202311/8759
128K 8K 2K
112LQFP
DT128302212/16891
DJ128212212/16891
DG128202212/16891
80QFP
DJ128212211/8759
DG128202211/8759
64K 4K 1K
112LQFP
DJ64 112112/16891
D64 102112/16891
80QFP
DJ64 112111/8759
D64 102111/8759
32K2K1K80QFPD32 102101/8759
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC9S12DG256MFUE

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
16-bit Microcontrollers - MCU BARRACUDA4 MOS13 L01Y
Lifecycle:
New from this manufacturer.
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