ADM483E
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RO
1
RE
2
DE
3
DI
4
V
CC
8
B
7
A
6
GND
5
ADM483E
TOP VIEW
(Not to Scale)
6012-002
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 RO Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low.
2
RE Receiver Output Enable. A low level enables the receiver output, RO. A high level places the receiver output in a high
impedance state.
3 DE
Driver Output Enable. A high level enables the driver differential outputs, A and B. A low level places the driver
differential outputs in a high impedance state.
4 DI
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high. A logic high on DI forces
A high and B low.
5 GND Ground Connection, 0 V.
6 A Noninverting Receiver Input A/Driver Output A.
7 B Inverting Receiver Input B/Driver Output B.
8 V
CC
Power Supply, 5 V ± 10%.
Table 5. Selection Table
Part No. Duplex Data Rate (kbps) Low Power Shutdown Tx/Rx Enable I
CC
(μA) No. of Tx/Rx on Bus ESD kV
ADM483E Half 250 Yes Yes 36 32 ±15
