MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
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Detailed Description
The MAX9242/MAX9244/MAX9246/MAX9254 deserialize
three LVDS serial-data inputs into 21 single-ended LVC-
MOS/LVTTL outputs. The outputs are programmable for
no spread or for a spread of ±2% or ±4%, relative to the
LVDS input clock frequency. The MAX9242/MAX9244/
MAX9254 operate at a parallel clock frequency of 16MHz
to 34MHz in DC-balanced mode and 20MHz to 40MHz in
non-DC-balanced mode. The MAX9246 operates at a
6MHz-to-18MHz parallel clock frequency in DC-balanced
mode and 8MHz-to-20MHz parallel clock frequency in
non-DC-balanced mode. DC-balanced or non-DC-bal-
anced operation is controlled by the DCB input. The
MAX9242 has a rising-edge strobe and the MAX9244/
MAX9246/MAX9254 have a falling-edge strobe.
DC Balance (DCB)
DC-balanced or non-DC-balanced operation is con-
trolled by the DCB input (see Table 1). In the non-DC-
balanced mode, each channel deserializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are deserialized every clock cycle (7 data bits + 2
DC-balanced bits). The highest serial-data rate on each
channel in DC-balanced mode is 34MHz x 9 = 306Mbps.
In non-DC-balanced mode, the maximum data rate is
40MHz x 7 = 280Mbps.
Data coding by the MAX9209/MAX9213 serializers (that
are companion devices to the MAX9242/MAX9244/
MAX9246/MAX9254 deserializers) limits the imbalance
of ones and zeros transmitted on each channel. If +1 is
assigned to each binary 1 transmitted and -1 is
assigned to each binary 0 transmitted, the variation in
the running sum of assigned values is called the digital
sum variation (DSV). The maximum DSV for the data
channels is 10. At most, 10 more zeros than ones, or 10
more ones than zeros, are ever transmitted. The maxi-
mum DSV for the clock channel is 5. Limiting the DSV
and choosing the correct coupling capacitors maintain
differential signal amplitude and reduces jitter due to
droop on AC-coupled links.
To obtain DC balance on the data channels, the serial-
izer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel-input data bits to indicate to the MAX9242/
MAX9244/MAX9246/MAX9254 deserializer whether the
data bits are inverted (see Figures 11 and 12). The
deserializer restores the original state of the parallel
data. The LVDS clock signal alternates duty cycles of
4/9 and 5/9 to maintain DC balance.
Spread-Spectrum Generator (SSG)
The MAX9242/MAX9244/MAX9246/MAX9254 single-
ended data and clock outputs are programmable for a
variation of ±2% or ±4% around the LVDS input clock fre-
quency. The modulation rate of the frequency variation is
32.48kHz for a 33MHz LVDS clock input and scales lin-
early with the input clock frequency (see Table 2). The
spread spectrum can also be turned off. The output
spread is controlled through the SSG input (see Table 3).
Table 1. DCB Function
