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9112BF-17LFT

P1-P3P4-P6P7-P8
4
ICS9112-17
0051K—11/02/04
Electrical Characteristics - OUTPUT
T
A
= 0 - 70°C; V
DD
= V
DDL
= 3.3 V +/-10%; C
L
= 20 - 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP
V
O
= V
D
D
*(0.5) 10 24
Ω
Output Impedance R
DSN
V
O
= V
D
D
*(0.5) 10 24
Ω
Output High Voltage V
OH
I
OH
= -8 mA 2.4 2.9 3.3 V
Output Low Voltage V
OL
I
OL
= 8 mA 0.25 0.4 V
Rise Time
1
T
r
V
OL
= 0.8 V, V
OH
= 2.0 V 1.2 2.0 ns
Fall Time
1
T
f
V
OH
= 2.0 V, V
OL
= 0.8 V 1.2 2.0 ns
PLL Lock Time1 tLOCK
Stable power supply, valid clock
presented on REF pin
1.0 ms
D
t
V
T
= 1.4V;Cl=30pF 40 50 60 %
D
t
V
T
= Vdd/2; Fout <66.6MHz 45 50 55 %
Tcyc-cyc at 66MHz , Loaded Outputs 250 ps
Tcyc-cyc >66MHz , Loaded Outputs 200 ps
Absolute Jitter
1
Tjabs 10000 cycles; Cl=30pF -100 70 100 ps
Jitter; 1-Sigma
1
Tj1s 10000 cycles; Cl=30pF 14 30 ps
Skew
1
T
sk
V
T
= 1.4 V (Window) Output to Output 250 ps
D
evice to Device Ske
w
1
Tdsk-Tdsk
Measured at VDD/2 on the CLKOUT
pins of devices
0700ps
Delay Input-Output
1
D
R1
V
T
= 1.4 V
0700ps
1
Guaranteed by design, not 100% tested in production.
Cycle to Cycle jitter
1
Duty Cycle
1
Electrical Characteristics - OUTPUT
T
A
= 0 - 70°C; V
DD
= V
DDL
= 5.0 V +/-10%; C
L
= 20 - 30 pF (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP
V
O
= V
DD
*(0.5) 10 24
Ω
Output Impedance R
DSN
V
O
= V
DD
*(0.5) 10 24
Ω
Output High Voltage V
OH
I
OH
= -8 mA 2.4 2.9 5.0 V
Output Low Voltage V
OL
I
OL
= 8 mA 0.25 0.4 V
Rise Time
1
T
r
V
OL
= 0.8 V, V
OH
= 2.0 V 0.8 1.5 ns
Fall Time
1
T
f
V
OH
= 2.0 V, V
OL
= 0.8 V 1.0 1.5 ns
PLL Lock Time
1
tLOCK
Stable power supply, valid clock
presented on REF pin
1.0 ms
Duty Cycle
1
D
t
V
T
= 1.4V;Cl=30pF 40 50 60 %
Tcyc-cyc at 66MHz , Loaded Outputs 250 ps
Tcyc-cyc >66MHz , Loaded Outputs 200 ps
Absolute Jitter
1
Tjabs 10000 cycles; Cl=30pF -100 60 100 ps
Jitter; 1-Si
g
ma
1
Tj1s 10000 c
y
cles; Cl=30pF 14 30 ps
Skew
1
T
sk
V
T
= 1.4 V (Window) Output to Output 250 ps
Device to Device
Skew
1
Tdsk-Tdsk
Measured at VDD/2 on the CLKOUT
pins of devices
0 700 ps
Delay Input-Output
1
D
R1
V
T
= 1.4 V
0 700 ps
1
Guaranteed by design, not 100% tested in production.
Cycle to Cycle jitter
1
5
ICS9112-17
0051K—11/02/04
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded
than CLKOUT, CLKA/B will lag the CLKOUT.
Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them
to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded
Equally
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
6
ICS9112-17
0051K—11/02/04
Application Suggestion:
ICS9112-17 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise
generated by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will
cause excess jitter to the outputs of ICS9112-17. Below is a recommended lay out to alleviate any addition noise. For
additional information on FT. layout, please refer to our AN07. The 0.1 uF capacitors should be connected as close as
possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line
stability.
33Ω
33Ω
33Ω
33Ω
10KΩ
0.1µF
VDD
GND
33Ω
33Ω
33Ω
33Ω
33Ω
10KΩ
0.1µF
VDD
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
FS2
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
FS1
P1-P3P4-P6P7-P8

9112BF-17LFT

Mfr. #:
Buy 9112BF-17LFT
Manufacturer:
IDT
Description:
Clock Buffer PC BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
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