Integrated
Circuit
Systems, Inc.
General Description Features
ICS9112-17
0051K—11/02/04
Block Diagram
Low Skew Output Buffer
Pin Configuration
• Zero input - output delay
• Frequency range 25 - 133 MHz (3.3V)
• High loop filter bandwidth ideal for Spread Spectrum
applications.
• Less than 200 ps cycle to cycle Jitter
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 16 pin, 150 mil SSOP & SOIC package
The ICS9112-17 is a high performance, low skew, low jitter
zero delay buffer. It uses a phase lock loop (PLL)
technology to align, in both phase and frequency, the REF
input with the CLKOUT signal. It is designed to distribute
high speed clocks in PC systems operating at speeds
from 25 to 133 MHz.
ICS9112-17 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS9112-17 has two banks of four outputs controlled
by two address lines. Depending on the selected address
line, bank B or both banks can be put in a tri-state mode.
In this mode, the PLL is still running and only the output
buffers are put in a high impedance mode. The test mode
shuts off the PLL and connects the input directly to the
output buffers (see table below for functionality).
The ICS9112-17 comes in a sixteen pin 150 mil SOIC or
16 pin SSOP package. In the absence of REF input, will
be in the power down mode. In this mode, the PLL is turned
off and the output buffers are pulled low. Power down mode
provides the lowest power consumption for a standby
condition.
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BKLC
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00 etatsirTetatsirTnevirDLLPN
01 nevirDetatsirTnevirDLLPN
10
LLP
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LLP
ssapyB
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LLP
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FERY
11 nevirDnevirDnevirDLLPN
Functionality
16 pin SSOP & SOIC
