MICRF011BN Datasheet MICRF011BM, MICRF011BM-TR, MICRF011BN | P7-P9

QwikRadio

December 1998b

MICRF011

MICRF011 Micrel

Functional Description

Please refer to “MICRF011 Block Diagram”. Identified in the

figure are the three principal functional blocks of the IC,

namely (1) UHF Downconverter, (2) OOK Demodulator, and

(3) Reference and Control. Also shown in the figure are two

capacitors (CTH, CAGC) and one timing component (CR),

usually a ceramic resonator. With the exception of a supply

decoupling capacitor, these are all the external components

needed with the MICRF011 to construct a complete UHF

receiver. Three control inputs are shown in the block

diagram, SEL0, SEL1 and SWEN. Through these logic

inputs the user can control the operating mode and

programmable functions of the IC. These inputs are CMOS

compatible, and are pulled-up on the IC.

Input SWEN selects the operating mode of the IC (FIXED

mode or SWP mode). When low, the IC is in FIXED mode,

and functions as a conventional superheterodyne receiver.

When SWEN is high, the IC is in SWP mode. In this mode,

while the topology is still superheterodyne, the local

oscillator (LO) is deterministically swept over a range of

frequencies at rates greater than the data rate. When

coupled with a peak-detecting demodulator, this technique

effectively increases the RF bandwidth of the MICRF011, so

the device can operate in applications where significant

Transmitter/Receiver frequency misalignment may exist.

[Note: The swept LO technique does not affect the IF

bandwidth, so noise performance is not impacted relative to

FIXED mode. In other words, the IF bandwidth is the same

(500kHz) whether the device is in FIXED or SWP mode.]

Due to limitations imposed by the LO sweeping process, the

upper limit on data rate in SWP mode is approximately

2.5kbps. Data rates beyond 10kbps are possible in FIXED

mode however.

Examples of SWP mode operation include applications

which utilize low-cost LC-based transmitters, whose transmit

frequency may vary up to ± 0.5% over initial tolerance,

aging, and temperature. In this (patent-pending) mode, the

LO frequency is varied in a prescribed fashion which results

in downconversion of all signals in a band approximately

1.5% around the transmit frequency. So the Transmitter

may drift up to ± 0.5% without the need to retune the

Receiver, and without impacting system performance. Such

performance is not achieved with currently available crystal-

based superheterodyne receivers, which can operate only

with SAW or crystal based transmitters.

[Note: In SWP mode only, a range penalty will occur in

installations where there exists a competing signal of

sufficient strength in this small frequency band of 1.5%

around the transmit frequency. This results from the fact

that sweeping the LO indiscriminately “sweeps” all signals

within the sweep range down into the IF band. This same

penalty also exists with super-regenerative type receivers,

as their RF bandwidth is also generally 1.5%. So any

application for a super-regenerative receiver is also an

application for the MICRF011 in SWP mode.]

For applications where the transmit frequency is accurately

set for other reasons (e.g., applications where a SAW

transmitter is used for its mechanical stability), the user may

choose to configure the MICRF011 as a standard

superheterodyne receiver (FIXED mode), mitigating the

aforementioned problem of a competing close-in signal.

This can be accomplished by tying SWEN to ground. Doing

so forces the on-chip LO frequency to a fixed value. In

FIXED mode, the ceramic resonator would be replaced with

a crystal. Generally, however, the MICRF011 can be

operated in SWP mode, using a ceramic resonator, with

either LC or CRYSTAL/SAW based transmitters, without

any significant range difference.

The inputs SEL0 and SEL1 control the Demodulator filter

bandwidth in four binary steps (625Hz-5000Hz in SWP,

1250Hz-10000Hz in FIXED mode), and the user must select

the bandwidth appropriate to his needs.

Rolloff response of the IF Filter is 5

order, while the

demodulator data filter exhibits a 2

order response.

Multiplication factor between the REFOSC frequency ft and

the internal Local Oscillator (LO) is 64.5X for FIXED mode,

and 64.25X for SWP mode (i.e., for ft = 6.00MHz in FIXED

mode, LO frequency = 6.00MHz * 64.5 = 387MHz).

Slicing Level and the CTH Capacitor

Extraction of the DC value of the demodulated signal for

purposes of logic-level data slicing is accomplished by

external capacitor CTH and the on-chip switched-cap

“resistor” RSC, indicated in the block diagram. The effective

resistance of RSC is 118kohms. The value of capacitor

CTH is easily calculated, once the slicing level time-constant

is chosen. Values vary somewhat with decoder type, data

pattern, and data rate, but typical Slicing Level time

constants range 5-50msec. Optimization of the CTH value

is required to maximize range, as discussed in “Application

Note 22, MICRF001 Theory of Operation”, section 6.4.

During quiet periods (i.e., no signal transmissions) the Data

Output (DO pin) transitions randomly based on noise. This

may present problems for some decoders. The most

common solution is to introduce a small offset (“Squelch”)

on the CTH pin so that noise does not trigger the internal

comparator. Usually 20-30mV is sufficient, and may be

introduced by connecting a several-Megohm resistor from

the CTH pin to either VSS or VDD, depending on the desired

offset polarity. Since the MICRF011 is an AGC’d receiver,

noise at the internal comparator input is always the same,

set by the AGC. So the squelch offset requirement does not

change as the local “ether” noise changes from installation

to installation. Note that introducing squelch will reduce

range modestly, so only introduce an amount sufficient to

“quiet” the output.

AGC Function and the CAGC Capacitor

The signal path has automatic gain control (AGC) to

increase input dynamic range. An external capacitor,

CAGC, must be connected to the CAGC pin of the device.

The ratio of decay-to-attack time-constant is fixed at 10:1

(i.e., the attack time constant is 1/10th the decay time

constant), and this ratio cannot be changed by the user.

However, the attack time constant is selectable by the user

through the value of capacitor CAGC.

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December 1998b

MICRF011

MICRF011 Micrel

[By adding resistance from the CAGC pin to VDDBB or

VSSBB in parallel with the CAGC capacitor, the ratio of

decay-to-attack time-constant may be varied, although the

value of such adjustments must be studied on a per-

application basis. Generally the design value of 10:1 is

adequate for the vast majority of applications.] See

“Application Note 22”.

To maximize system range, it is important to keep the AGC

control voltage ripple low, preferably under 10mVpp once

the control voltage has attained its quiescent value. For this

reason capacitor values ≥ 0.47uF are recommended.

Reference Oscillator (REFOSC) and External Timing

Element

All timing and tuning operations on the MICRF011 are

derived from the REFOSC function. This function is a

single-pin Colpitts-type oscillator. The user may handle this

pin in one of three possible ways:

(1) connect a ceramic resonator, or

(2) connect a crystal, or

(3) drive this pin with an external timing signal.

The third approach is attractive for further lowering system

cost if an accurate reference signal exists elsewhere in the

system (e.g., a reference clock from a crystal or ceramic

resonator-based microprocessor). An externally applied

signal should be AC-coupled, and resistively-divided down

(or otherwise limited) to approximately 0.5Vpp. The specific

reference frequency required is related to the system

transmit frequency, and the operating mode of the device as

set by the SWEN control pin. See “Application Note 22,

MICRF001 Theory of Operation” for a discussion of

frequency selection and accuracy requirements.

MICRF011 Frequency and Capacitor Selection

Selection of the REFOSC frequency ft, Slicing Level (CTH)

capacitor, and AGC capacitor are briefly summarized in this

section. Please see Application Note 22 for complete

details.

1. Selecting REFOSC Frequency ft (FIXED Mode)

As with any superheterodyne receiver, the difference

between the (internal) Local Oscillator (LO) frequency flo

and the incoming Transmit frequency ftx must ideally equal

the IF Center frequency. Equation (1) may be used to

compute the appropriate flo for a given ftx:

flo = ftx ± 1.064 * (ftx / 390) (1)

where ftx and flo are in MHz. Note that two values of flo

exist for any given ftx, distinguished as “high-side mixing”

and “low-side mixing”, and there is generally no preference

of one over the other.

After choosing one of the two acceptable values of flo, use

equation (2) to compute the REFOSC frequency ft:

ft = flo / 64.5. (2)

Here ft is in MHz. Connect a crystal of frequency ft to the

REFOSC pin of the MICRF011. 4 decimal-place accuracy

on the frequency is generally adequate. The following table

identifies ft for some common Transmit frequencies when

the MICRF011 is operated in FIXED mode.

Transmit Freq. ftx (MHz) REFOSC Freq. ft (MHz)

315

418

433.92

4.8970

6.4983

6.7458

2. Selecting REFOSC Frequency ft (SWP Mode)

Selection of REFOSC frequency ft in SWP mode is much

simpler than in FIXED mode, due to the LO sweeping

process. Further, accuracy requirements of the frequency

reference component are significantly relaxed.

In SWP mode, ft is given by equation (3):

ft = ftx / 64.25. (3)

Connect a ceramic resonator of frequency ft to the REFOSC

pin of the MICRF011. 2-decimal place accuracy is generally

adequate. (A crystal may also be used if desired, but may

be necessary to reduce the Rx frequency ambiguity if the Tx

frequency ambiguity is excessive. See Application Note 22

for further details.)

3. Selecting Capacitor CTH

First step in the process is selection of a Data Slicing Level

timeconstant. This selection is strongly dependent on

system issues, like system decode response time and data

code structure (e.g., existence of data preamble, etc.). This

issue is too broad to discuss here, and the interested reader

should consult the Application Note 22.

Source impedance of the CTH pin is given by equation (4),

where ft is in MHz:

Rsc = 118kΩ * (4.90 / ft). (4)

Assuming that a Slicing Level Timeconstant TC has been

established, capacitor CTH may be computed using

equation (5):

CTH = TC / Rsc. (5)

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December 1998b

MICRF011

MICRF011 Micrel

3. Selecting CAGC Capacitor

Selection of CAGC is dictated by minimizing the ripple on

the AGC control voltage, by using a sufficiently large

capacitor. It is Micrel’s experience that CAGC should be in

the vicinity of 0.47µF to 4.7µF. Large capacitor values

should be carefully considered, as this determines the time

required for the AGC control voltage to settle from a

completely discharged condition. AGC settling time from a

completely discharged (0-volt) state is given approximately

by equation (6):

∆T = (1.333 * CAGC) – 0.44 (6)

where CAGC is in microfarads, and ∆T is in seconds.

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF011 is

shown in Figures 1 through 6. Specific information

regarding each of these circuits is discussed in the following

sub-paragraphs. Not shown are ESD protection diodes

which are applied to all input and output pins.

1. ANT Pin

The ANT pin is internally AC-coupled via a 3pF capacitor, to

an RF N-channel MOSFET, as shown in Figure 1.

Impedance on this pin to VSS is quite high at low

frequencies, and decreases as frequency increases. In the

UHF frequency range, the device input can be modeled as

6.3kΩ in parallel with 2pF (pin capacitance) shunt to

VSSRF.

2. CTH Pin

Figure 2 illustrates the CTH pin interface circuit. CTH pin is

driven from a P-channel MOSFET source-follower biased

with approximately 10µA of bias current. Transmission

gates TG1 and TG2 isolate the 6.9pF capacitor. Internal

control signals PHI1/PHI2 are related in a manner such that

the impedance across the transmission gates looks like a

“resistance” of approximately 118kΩ. The DC potential on

the CTH pin is approximately 1.6V.

3. CAGC Pin

Figure 3 illustrates the CAGC pin interface circuit. The AGC

control voltage is developed as an integrated current into a

capacitor CAGC. The attack current is nominally 15µA,

while the decay current is a 1/10th scaling of this,

approximately 1.5µA. Signal gain of the RF/IF strip inside

the IC diminishes as the voltage on CAGC decreases. By

simply adding a capacitor to CAGC pin, the attack/decay

time constant ratio is fixed at 1:10. Further discussion on

setting the attack time constant is found in “Application Note

22, MICRF001 Theory of Operation”, section 6.5.

Modification of the attack/decay ratio is possible by adding

resistance from CAGC pin either to VDDBB or VSSBB, as

desired.

4. DO Pin

The output stage for the Data Comparator (DO pin) is shown

in Figure 4. The output is a 10µA push-10µA pull, switched

current stage. Such an output stage is capable of driving

CMOS-type loads. An external buffer-driver is

recommended for driving high capacitance loads.

5. REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input

impedance is quite high (200kΩ). This is a Colpitts

oscillator, with internal 30pF capacitors. This input is

intended to work with standard ceramic resonators,

connected from this pin to VSSBB, although a crystal may

be used instead, where greater frequency accuracy is

required. The resonators should not contain integral

capacitors, since these capacitors are contained inside the

IC. Externally applied signals should be AC-coupled,

amplitude limited to approximately 0.5Vpp. The nominal DC

bias voltage on this pin is 1.4V.

6. Control Inputs (SEL0, SEL1, SWEN)

Control input circuitry is shown in Figure 6. The standard

input is a logic inverter constructed with minimum geometry

MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a large

channel length device which functions essentially as a

“weak” pullup to VDDBB. Typical pullup current is 5µA,

leading to an impedance to the VDDBB supply of typically

1MΩ.

Figure 1 ANT Pin

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