MAX3040ESE+T Datasheet MAX3045BESE+T, MAX3040EWE+, MAX3041EUE+ | P7-P9

MAX3040–MAX3045

±10kV ESD-Protected, Quad 5V RS-485/RS-422

Transmitters

_______________________________________________________________________________________ 7

Detailed Description

The MAX3040–MAX3045 are quad RS-485/RS-422 trans-

mitters. They operate from a single +5V power supply

and are designed to give optimum performance when

used with the MAX3093E/MAX3095 5V quad RS-485/

RS-422 receivers or MAX3094E/MAX3096 3V quad

RS-485/RS-422 receivers. The MAX3040–MAX3045 only

need 1mA of operating supply current and consume 2nA

when they enter a low-power shutdown mode. The

MAX3040–MAX3045 also feature a hot-swap capability

allowing line insertion without erroneous data transfer.

The MAX3042B/MAX3045B are capable of transferring

data up to 20Mbps, the MAX3041/MAX3044 for data

rates up to 2.5Mbps, and the MAX3040/MAX3043 for

data rates up to 250kbps. All transmitter outputs are pro-

tected to ±10kV using the Human Body Model.

±10kV ESD Protection

As with all Maxim devices, ESD-protection structures

are incorporated on all pins to protect against electro-

static discharges (ESD) encountered during handling

and assembly. The MAX3040–MAX3045 transmitter

outputs have extra protection against electrostatic dis-

charges found in normal operation. Maxim’s engineers

have developed state-of-the-art structures to protect

these pins against the application of ±10kV ESD

(Human Body Model), without damage.

ESD Test Conditions

ESD performance depends on a number of conditions.

Contact Maxim for a reliability report that documents

test setup, methodology, and results.

Human Body Model

Figure 6a shows the Human Body Model, and Figure

6b shows the current waveform it generates when dis-

charged into low impedance. This model consists of a

100pF capacitor charged to the ESD voltage of interest,

which is then discharged into the device through a

1.5kΩ resistor.

Figure 1. Driver DC Test Circuit

DIFF

Figure 2. Driver Timing Test Circuit

-V

1.5V

PLH

1/2 V

10%

90%

PHL

1.5V

1/2 V

10%

DIFF

= V (Y) - V (Z)

DIFF

SKEW = |

PLH

- t

PHL

Figure 3. Driver Propagation Delays

OUTPUT NORMALLY LOW

OUTPUT NORMALLY HIGH

Y, Z

1.5V 1.5V

+0.5V

-0.5V

2.5V

ZL(SHDN)

, t

ZH(SHDN)

, t

Figure 5. Driver Enable and Disable Times

OUTPUT

UNDER TEST

Figure 4. Driver Enable/Disable Timing Test Load

Machine Model

The Machine Model for ESD testing uses a 200pF stor-

age capacitor and zero-discharge resistance. It mimics

the stress caused by handling during manufacturing

and assembly. Of course, all pins (not just RS-485

inputs) require this protection during manufacturing.

Therefore, the Machine Model is less relevant to the I/O

ports than are the Human Body Model.

±4kV Electrical Fast Transient/Burst Testing

(IEC 1000-4-4)

IEC 1000-4-4 Electrical Fast Transient/Burst (EFT/B) is

an immunity test for the evaluation of electrical and

electronic systems during operating conditions. The

test was adapted for evaluation of integrated circuits

with power applied. Repetitive fast transients with

severe pulsed EMI were applied to signal and control

ports. Over 15,000 distinct discharges per minute are

sent to each interface port of the IC or equipment under

test (EUT) simultaneously with a minimum test duration

time of one minute. This simulates stress due to dis-

placement current from electrical transients on AC

mains, or other telecommunication lines in close prox-

imity. Short rise times and very specific repetition rates

are essential to the validity of the test.

Stress placed on the EUT is severe. In addition to the

controlled individual discharges placed on the EUT,

extraneous noise and ringing on the transmission line

can multiply the number of discharges as well as

increase the magnitude of each discharge. All cabling

was left unterminated to simulate worst-case reflections.

The MAX3040–MAX3045 were setup as specified in

IEC 1000-4-4 and the Typical Operating Circuit of this

data sheet. The amplitude, pulse rise time, pulse dura-

tion, pulse repetition period, burst duration, and burst

period (Figure 8) of the burst generator were all verified

with a digital oscilloscope according to the specifica-

tions in IEC 1000-4-4 sections 6.1.1 and 6.1.2. A simpli-

fied diagram of the EFT/B generator is shown in Figure

7. The burst stresses were applied to Y1–Y4 and Z1–Z4

simultaneously.

IEC 1000-4-4 provides several levels of test severity

(see Table 1). The MAX3040–MAX3045 pass the 4000V

stress, a special category “X” beyond the highest level

for severe (transient) industrial environments for

telecommunication lines.

MAX3040–MAX3045

±10kV ESD-Protected, Quad 5V RS-485/RS-422

Transmitters

8 _______________________________________________________________________________________

CHARGE-CURRENT

LIMIT RESISTOR

DISCHARGE

RESISTANCE

STORAGE

CAPACITOR

100pF

1MΩ

1.5kΩ

HIGH-

VOLTAGE

SOURCE

DEVICE

UNDER

TEST

Figure 6a. Human Body ESD Test Model

100%

90%

36.8%

TIME

CURRENT WAVEFORM

PEAK-TO-PEAK RINGING

(NOT DRAWN TO SCALE)

10%

AMPERES

Figure 6b. Human Body Model Current Waveform

ON I/O,

SIGNAL, DATA

AND CONTROL

PORTS

EFT

LEVEL

PEAK

VOLTAGE

REPETITION

RATE (kHz)

INDUSTRIAL

ELECTRO-

MAGNETIC

ENVIROMENT

1 250 5 Well protected

2 500 5 Protected

3 1000 5

Typical

4 2000 5

Severe

X 4000 5

MAX3040–MAX3045

Table 1. Test Severity Levels for

Communication Lines

MAX3040–MAX3045

±10kV ESD-Protected, Quad 5V RS-485/RS-422

Transmitters

_______________________________________________________________________________________ 9

IEC 1000-4-4 Burst/Electrical Fast

Transient Test Levels

(For Communication Lines)

The stresses are applied while the MAX3040–MAX3045

are powered up. Test results are reported as:

1) Normal performance within the specification limits.

2) Temporary degradation or loss of function or perfor-

mance which is self-recoverable.

3) Temporary degradation, loss of function or perfor-

mance requiring operator intervention, such as sys-

tem reset.

4) Degradation or loss of function not recoverable due

to damage.

The MAX3040–MAX3045 meets classification 2 listed

above. Additionally, the MAX3040–MAX3045 will not

latchup during the IEC burst stress events.

Hot-Swap Capability

Hot-Swap Inputs

When circuit boards are plugged into a “hot” back-

plane, there can be disturbances to the differential sig-

nal levels that could be detected by receivers

connected to the transmission line. This erroneous data

could cause data errors to an RS-485/RS-422 system.

To avoid this, the MAX3040–MAX3045 have hot-swap

capable inputs.

When a circuit board is plugged into a “hot” backplane

there is an interval during which the processor is going

through its power-up sequence. During this time, the

processor’s output drivers are high impedance and will

be unable to drive the enable inputs of the

MAX3040–MAX3045 (EN, EN, EN_) to defined logic lev-

els. Leakage currents from these high impedance dri-

vers, of as much as 10µA, could cause the enable

inputs of the MAX3040–MAX3045 to drift high or low.

Additionally, parasitic capacitance of the circuit board

could cause capacitive coupling of the enable inputs to

either GND or V

. These factors could cause the

enable inputs of the MAX3040–MAX3045 to drift to lev-

els that may enable the transmitter outputs (Y_ and Z_).

To avoid this problem, the hot-swap input provides a

method of holding the enable inputs of the

MAX3040–MAX3045 in the disabled state as V

ramps up. This hot-swap input is able to overcome the

leakage currents and parasitic capacitances that may

pull the enable inputs to the enabled state.

Hot-Swap Input Circuitry

In the MAX3040–MAX3045 the enable inputs feature

hot-swap capability. At the input there are two NMOS

devices, Q1 and Q2 (Figure 9). When V

is ramping

up from 0, an internal 10µs timer turns on Q2 and sets

the SR latch, which also turns on Q1. Transistors Q2, a

700µA current sink, and Q1, an 85µA current sink, pull

EN to GND through a 5.6kΩ resistor. Q2 is designed to

pull the EN input to the disabled state against an exter-

nal parasitic capacitance of up to 100pF that is trying to

enable the EN input. After 10µs, the timer turns Q2 off

and Q1 remains on, holding the EN input low against

three-state output leakages that might enable EN. Q1

remains on until an external source overcomes the

U = HIGH-VOLTAGE SOURCE

= CHARGING RESISTOR

= ENERGY STORAGE CAPACITOR

= PULSE DURATION SHAPING RESISTOR

= IMPEDANCE MATCHING RESISTOR

= DC BLOCKING CAPACITOR

SPARK GAP

50Ω

COAXIAL

OUTPUT

Figure 7. Simplified Circuit Diagram of a Fast Transient/Burst

Generator

REPETITION PERIOD (DEPENDS ON THE TEST VOLTAGE LEVER,

IN CONFORMITY WITH THE VALUES INDICATED IN 6.1.2).

BURST

BURST DURATION

BURST PERIOD 300ms

PULSE

15ms

Figure 8. General Graph of a Fast Transient Burst

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

MAX3040ESE+T

Mfr. #:

Buy MAX3040ESE+T

Manufacturer:

Maxim Integrated

Description:

RS-422/RS-485 Interface IC Quad 5V RS-485 RS-422 Trx

Lifecycle:

New from this manufacturer.

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