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WMS7170010S

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
WMS7170 / 7171
Publication Release Date: July 2003
- 13 - Revision 1.0
TABLE 12 – ELECTRICAL CHARACTERISTICS (Packaged parts) – Cont’d
PARAMETERS SYMBOL MIN. TYP. MAX. UNITS CONDITIONDS
[5]
Input Leakage Current I
LI
-1 +1 uA
CS =V
DD
,Vin=Vss ~ V
DD
Output Leakage Current
I
Lo
-1 +1 uA
CS =V
DD
,Vin=V
SS
~ V
DD
Input Capacitance
[1]
C
IN
25 pF V
DD
=5V, fc = 1Mhz
Output Capacitance
[1]
C
OUT
25 pF V
DD
=5V, fc = 1Mhz
Power Requirements
Operating Voltage V
DD
2.7 5.5 V
Operating Current I
DDR
, I
DDW
1 2 mA All operations
I
SA
[3]
0.5 1 mA
Buffer = ON
CS = HIGH, no load
Standby Current
I
SB
[4]
0.1 1 uA
Buffer = OFF
CS = HIGH, no load
Power Supply Rejection
Ratio
PSRR 1 LSB/V
V
DD
=5V±10%, Wiper at center
Notes:
[1]
Not subject to production test.
[2]
LSB = (R
A
/V
A
– R
B
/V
B
) / (T - 1); DNL = (V
i
- V
i+1
) / LSB + 1 (if increment) or = (V
i
-
V
i+1
) / LSB - 1 (if decrement); INL = (V
i
- i*LSB) / LSB; where i = [0, (T -1)] and T =
# of taps of the device.
[3]
WMS7171 only.
[4]
WMS7170 only.
[5]
Conditions: V
CC
= 2.7 to 5.5V, T = 25ºC and timing measured at 50% level, unless stated.
[6]
Only guarantee by design.
[7]
R
total
= end-to-end resistance.
WMS7170 / 7171
- 14 -
10.1 TEST CIRCUITS
FIGURE 4 – TEST CIRCUITS
Potentiometer divider nonlinearit
y
error
test circuit
INL, DNL
*Assume infinite in
p
ut im
p
edance
V+
V
MS
*
V+
= V
DD
1LSB
=
V
+
/
9
9
WMS71xx
V
A
V
B
V
W
Resistor
p
osition nonlinearit
y
error test
circuit (Rheostat Operation: R-INL, R-DNL)
*Assume infinite in
p
ut im
p
edance
No Connection
V
MS
*
WMS71xx
W
R
A
R
B
R
W
I
W
WMS71xx
Wi
p
er resistance test circuit
*Assume infinite in
p
ut im
p
edance
V
MS
*
WMS71xx
V
A
V
B
V
W
I
W
I
W
= V
DD
/R
Total
R
W
= V
MS
/I
W
Power supply sensitivity test circuit (PSS, PSRR)
*Assume infinite in
p
ut im
p
edance
+
V
V
A
V
B
V
W
V
MS
*
PSRR
(
dB
)
= 20LOG
(
)
∆
V
MS
∆
V
DD
PSS
(
%/%
)
=
∆
V
MS
∆
V
DD
WMS71xx
V
A
V
B
V
W
V
IN
~
+5V
2.5V DC
Offset
V
OUT
Ca
p
acitance test circuit
V
A
V
B
WMS71xx
V
W
V
IN
~
+5V
2.5V DC
V
OUT
OFFSET
GND
Gain vs. fre
q
uenc
y
test circuit
V
A
V
A
= V
DD
V
+
= V
DD
± 10%
WMS7170 / 7171
Publication Release Date: July 2003
- 15 - Revision 1.0
11. TYPICAL APPLICATION CIRCUITS
Vin
V
OUT
= - V
IN
A
B
R
R
R
A
= , R
B
=
R
AB
= Total resistance of potentiometer
W = Wiper setting for WMS71XX
FIGURE 5 – PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7170/7171
V
OUT
= V
IN
(1+
A
B
R
R
)
R
A
= , R
B
=
R
AB
= Total resistance of potentiometer
W = Wiper setting for WMS71XX
FIGURE 6 – PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7170/7171
OP
A
MP
_
V
OUT
WMS71XX
+
OP
A
MP
V
IN
V
OUT
WMS71XX
_
R
A
R
B
R
A
R
B
+
R
AB
(100-W)
100 100
R
AB
*W
R
AB
(100-W)
100 100
R
AB
*W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

WMS7170010S

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IC POT DGTL 10K 100TAPS 8-SOIC
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