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CS4192XDWF16

P1-P3P4-P6P7-P8
CS4192
http://onsemi.com
4
PIN FUNCTION DESCRIPTION
PACKAGE PIN #
16 Lead SOIC Wide
PIN SYMBOL FUNCTION
1 SIN− Negative output for SINE coil.
2 SIN+ Positive output SINE coil.
3 V
BB
Analog supply. Nominally 13.5 V.
4, 5, 12, 13 GND Ground.
6 SI Serial data input. Data present at the rising edge of the clock signal is shifted into
the internal shift register.
7 V
CC
5.0 V logic supply. The internal registers and latches are reset by a POR generated
by the rising edge of the voltage on this pin.
8 OE Controls the state of the output buffers. A logic low on this pin turns them off.
9 SCLK Serial clock for shifting in/out of data. Rising edge shifts data on SI into the shift
register and the falling edge changes the data on SO.
10 CS When high allows data at SI to be shifted into part with the rising edges of SCLK.
The falling edge transfers the shift register contents into the DAC and multiplexer
to update the output buffers. The falling edge also reenables the output drivers if
they have been disabled by a fault.
11 ST STATUS reflects the state of the outputs and is low anytime the outputs are disabled,
either by OE or the internal protection circuitry. Requires external pullup resistor.
14 SO Serial data output. Existing 10−bit data is shifted out when new data is shifted in.
Allows cascading of multiple devices on common serial port.
15 COS− Negative output for COSINE coil.
16 COS+ Positive output for COSINE coil.
ORDERING INFORMATION
Device Package Shipping
†
CS4192XDWF16 SOIC−16 WB 47 Units / Rail
CS4192XDWF16G SOIC−16 WB
(Pb−Free)
47 Units / Rail
CS4192XDWFR16 SOIC−16 WB 1000 Units / Reel
CS4192XDWFR16G SOIC−16 WB
(Pb−Free)
1000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
CS4192
http://onsemi.com
5
APPLICATIONS INFORMATION
THEORY OF OPERATION
The SACD is for interfacing between a microcontroller or
microprocessor and air−core meter movements commonly
used in automotive vehicles for speedometers and
tachometers. These movements are built using two coils
placed at a 90° orientation to each other. A magnetized disc
floats in the middle of the coils and responds to the magnetic
field generated by each coil. The disc has a shaft attached to
it that protrudes out of the assembly. A pointer indicator is
attached to this shaft and in conjunction with a separate
printed scale displays the vehicle’s speed or the engine’s
speed.
The disc (and pointer) respond to the vector sum of the
voltages applied to the coils. Ideally, this relationship
follows a sine/cosine equation. Since this is a transcendental
and non−linear function, devices of this type use an
approximation for this relationship. The SACD uses a
tangential algorithm as shown in Figure 2. Only one output
varies in any 45 degree range.
S
IN+
O
utput
Max(128)
S
IN−
O
utput
C
OS+
O
utput
C
OS−
O
utput
Max(128)
Max(128)
Max(128)
Min(0)
Min(0)
Min(0)
Min(0)
0° 45° 90° 135° 180° 225° 270° 315° 360°
000 001 010 011 100 101 110 111 00
0
MUX bits (D9−D7)
Degrees of Rotation
Figure 2. SIN, COS Outputs
Quadrant I
q + Tan
−1
ƪ
V
SIN)
* V
SIN*
V
COS)
* V
COS*
ƫ
For q + 0.176°to 44.824° :
V
SIN
+ Tanq 0.748 V
BB
V
COS
+ 0.748 V
BB
For q + 45.176°to 89.824° :
V
SIN
+ 0.748 V
BB
V
COS
+ Tan(90° * q) 0.748 V
BB
Quadrant II
q + 180°−Tan
−1
ƪ
V
SIN)
* V
SIN*
V
COS)
* V
COS*
ƫ
For q + 90.176°to 134.824° :
V
SIN
+ 0.748 V
BB
V
COS
+*Tan (q * 90°) 0.748 V
BB
For q + 135.176°to 179.824° :
V
SIN
+ Tan(180° * q) 0.748 V
BB
V
COS
+*0.748 V
BB
Quadrant III
q + 180° ) Tan
−1
ƪ
V
SIN)
* V
SIN*
V
COS)
* V
COS*
ƫ
For q + 180.176°to 224.824° :
V
SIN
+*Tan (q * 180°) 0.748 V
BB
V
COS
+*0.748 V
BB
For q + 225.176°to 269.824° :
V
SIN
+*0.748 V
BB
V
COS
+*Tan (270° * q) 0.748 V
BB
Quadrant IV
q + 360° * Tan
−1
ƪ
V
SIN)
* V
SIN*
V
COS)
* V
COS*
ƫ
For q + 270.176°to 314.824° :
V
SIN
+*0.748 V
BB
V
COS
+ Tan(q * 270°) 0.748 V
BB
For q + 315.176° * 359.824° :
V
SIN
+*Tan (360° * q) 0.748 V
BB
V
COS
+ 0.748 V
BB
CS4192
http://onsemi.com
6
II
I
III
IV
270°
V
SIN−
V
SIN+
90°
V
COS−
V
COS+
180°
360/0°
0.748 V
BB
0.748 V
BB
0.748 V
BB
0.748 V
BB
q
Figure 3. Gauge Response
To drive the gauge’s pointer to a particular angle, the
microcontroller sends a 10−bit digital word into the serial
port. These 10 bits are divided as shown in Figure 4.
G
auge
(
360°)
MSB LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D9−D7 select
which octant
Divides a 45° octant into 128 equal parts to
achieve a 0.35° resolution Code 0−127
10
Figure 4. Definition of Serial Word
However, from a software programmers viewpoint, a
360° circle is divided into 1024 equal parts of 0.35° each.
Table 1 shows the data associated with the 45° divisions of
the 360° driver.
Table1. Nominal Output (V
BB
= 14 V)
Input Code
(Decimal)
Ideal
Degrees
Nominal
Degrees
V
SIN
(V)
V
COS
(V)
0 0 0.176 0.032 10.476
128 45 45.176 10.476 10.412
256 90 90.176 10.476 −0.032
384 135 135.176 10.412 −10.476
512 180 180.176 −0.032 −10.476
640 225 225.176 −10.476 −10.412
768 270 270.176 −10.476 0.032
896 315 315.176 −10.476 10.476
1023 359.65 359.826 −0.032 10.476
The 10 bits are shifted into the device’s shift register MSB
first using an SPI compatible scheme. This method is shown
in Figure 5. The CS must be high and remain high for SCLK
to be enabled. Data on SI is shifted in on the rising edge of
the synchronous clock signal. Data in the shift register
changes at SO on the falling edge of SCLK. This
arrangement allows the cascading of devices. SO is always
enabled. Data shifts through without affecting the outputs
until CS is brought low. At this time the internal DAC is
updated and the outputs change accordingly.
CS
SI
SCLK
SO
SI
(Setup)
SI
(Hold)
SI
(tpd)
SO
(Rise,
Fall)
10% − 90%
CS
Hold
CS
Setup
Figure 5. Serial Data Timing Diagram
Figure 6 shows the power−up sequence for the CS4192.
Note the IC requires a pulse on the Chip Select (CS) pin to
clear the Status Fault (ST) after power up. OE must be high
before the falling edge of CS to enable the output buffers.
V
CC
CS
SI
OE
ST
10
Bits
10
Bits
OUTPUTS
ENABLED
Registers
set to zero
Registers
set to zero
OUTPUTS
ENABLED
Figure 6. Power Up Sequence
P1-P3P4-P6P7-P8

CS4192XDWF16

Mfr. #:
Buy CS4192XDWF16
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers Single Air Core
Lifecycle:
New from this manufacturer.
Delivery:
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