PCA9675 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 3 October 2011 22 of 34
NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt
13. Dynamic characteristics
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[4] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
f
.
[5] C
b
= total capacitance of one bus line in pF.
[6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
Table 6. Dynamic characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Standard mode
I
2
C-bus
Fast mode
I
2
C-bus
Fast mode Plus
I
2
C-bus
Unit
Min Max Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 0 1000 kHz
t
BUF
bus free time between a
STOP and START condition
4.7 - 1.3 - 0.5 - s
t
HD;STA
hold time (repeated) START
condition
4.0 - 0.6 - 0.26 - s
t
SU;STA
set-up time for a repeated
START condition
4.7 - 0.6 - 0.26 - s
t
SU;STO
set-up time for STOP
condition
4.0 - 0.6 - 0.26 - s
t
HD;DAT
data hold time 0 - 0 - 0 - ns
t
VD;ACK
data valid acknowledge time
[1]
0.3 3.45 0.1 0.9 0.05 0.45 s
t
VD;DAT
data valid time
[2]
300 - 50 - 50 450 ns
t
SU;DAT
data set-up time 250 - 100 - 50 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - 0.5 - s
t
HIGH
HIGH period of the SCL
clock
4.0 - 0.6 - 0.26 - s
t
f
fall time of both SDA and
SCL signals
[3][4]
-30020+0.1C
b
[5]
300 - 120 ns
t
r
rise time of both SDA and
SCL signals
- 1000 20 + 0.1C
b
[5]
300 - 120 ns
t
SP
pulse width of spikes that
must be suppressed by the
input filter
[6]
-50 - 50-50ns
Port timing; C
L
100 pF (see Figure 14 and Figure 15)
t
v(Q)
data output valid time - 4 - 4 - 4 s
t
su(D)
data input set-up time 0 - 0 - 0 - s
t
h(D)
data input hold time 4 - 4 - 4 - s
Interrupt timing; C
L
100 pF (see Figure 14 and Figure 15)
t
v(D)
data input valid time - 4 - 4 - 4 s
t
d(rst)
reset delay time - 4 - 4 - 4 s
