ADM8696/ADM8697
–10–
TYPICAL APPLICATIONS
ADM8696
Figure 18 shows the ADM8696 in a typical power monitoring,
battery backup application. V
OUT
powers the CMOS RAM.
Under normal operating conditions with V
CC
present, V
OUT
is
internally connected to V
CC
. If a power failure occurs, V
CC
will
decay and V
OUT
will be switched to V
BATT
, thereby maintaining
power for the CMOS RAM.
Power Fail RESET
The V
CC
power supply is also monitored by the Low Line In-
put, LL
IN
. A RESET pulse is generated when LL
IN
falls below
1.3 V.
RESET will remain low for 50 ms after LL
IN
returns
above 1.3 V. This allows for a power-on reset and prevents re-
peated toggling of
RESET if the V
CC
power supply is unstable.
Resistors R3 and R4 should be chosen to give the desired V
CC
reset threshold.
Watchdog Timer
The Watchdog Timer Input (WDI) monitors an I/O line from
the µP system. This line must be toggled once every 1.6 s to
verify correct software execution. Failure to toggle the line indi-
cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
If the watchdog timer is not needed the WDI input should be
left floating.
Power Fail Detector
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network R1 and R2. This input is intended as
an early warning power fail input. The voltage on the PFI input
is compared with a precision 1.3 V internal reference. If the in-
put voltage drops below 1.3 V, a power fail output (PFO) signal
is generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold volt-
age V
T
. The threshold should be set at a higher voltage than the
RESET threshold so there is sufficient time available to com-
plete the shutdown procedure before the processor is RESET
and power is lost.
ADM8696
R2
R1
PFO
+5V
V
CC
CMOS RAM
POWER
I/O LINE
µP NMI
µP SYSTEM
µP POWER
V
OUT
WDI
GND
PFI
V
BATT
BATTERY
RESET
µP RESET
+
R4
R3
LL
IN
RESET
Figure 18a. ADM8696 Typical Application Circuit A
Figure 18b shows a similar application for the ADM8696 but in
this case the PFI input monitors the unregulated input to the
7805 voltage regulator. This gives an earlier warning of an im-
pending power failure. It is useful with processors operating at
low speeds or where there are a significant number of house-
keeping tasks to be completed before the power is lost.
ADM8696
R2
R1
PFO
INPUT
POWER
V
CC
V
OUT
GND
PFI
V
BATT
0.1µF
3V
BATTERY
RESET
OSC IN
OSC SEL
SYSTEM STATUS
INDICATORS
LOW LINE
CMOS RAM
I/O LINE
NMI
RESET
A0–A15
µP
BATT
ON
NC
V
CC
LL
IN
WDI
µP
POWER
RESET
R4
R3
7805
WDO
0.1µF
Figure 18b. ADM8696 Typical Application Circuit B
This application also shows an optional external transistor that
may be used to provide in excess of 100 mA current on V
OUT
.
When V
CC
is higher than V
BATT
, the BATT ON output goes
low, providing 25 mA of base drive for the external PNP transis-
tor. The maximum current available is dependent on the power
rating of the external transistor.
RAM Write Protection
The ADM8697 CE
OUT
line drives the Chip Select inputs of the
CMOS RAM.
CE
OUT
follows CE
IN
as long as LL
IN
is above the
reset threshold. If LL
IN
falls below the reset threshold, CE
OUT
goes high, independent of the logic level at CE
IN
. This prevents
the microprocessor from writing erroneous data into RAM dur-
ing power-up, power-down, brownouts and momentary power
interruptions.
