OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADM8697ARW

P1-P3P4-P6P7-P9P10-P12P13-P13
ADM8696/ADM8697
–7–
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the +5 V power supply falls below
the reset threshold.
PFO is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shut-
down procedure executed before power is lost.
ADM869x
POWER
FAIL
INPUT
R2
INPUT
POWER
POWER
FAIL
OUTPUT
R1
PFO
1.3V
Figure 7. Power Fail Comparator
Table II. Input and Output Status In Battery Backup Mode
Signal Status
V
OUT
(ADM8696) V
OUT
is connected to V
BATT
via an
internal PMOS switch.
RESET Logic low.
RESET Logic high. The open circuit output voltage is
equal to V
OUT
.
LOW LINE Logic low.
BATT ON (ADM8696) Logic high. The open circuit volt-
age is equal to V
OUT
.
WDI WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and V
OUT
. The input voltage
does not affect supply current.
WDO Logic high. The open circuit voltage is equal to
V
OUT
.
PFI The Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
PFO Logic low.
CE
IN
CE
IN
is ignored. It is internally disconnected
from its internal pull-up and does not source or
sink current as long as its input voltage is be-
tween GND and V
OUT
. The input voltage does
not affect supply current.
CE
OUT
Logic high. The open circuit voltage is equal to
V
OUT
.
OSC IN OSC IN is ignored.
OSC SEL OSC SEL is ignored.
CE Gating and RAM Write Protection (ADM8697)
The ADM8697 contains memory protection circuitry that
ensures the integrity of data in memory by preventing write
operations when LL
IN
is below the threshold voltage. When
LL
IN
is greater than 1.3 V, CE
OUT
is a buffered replica of CE
IN
,
with a 2 ns propagation delay. When LL
IN
falls below the 1.3 V
threshold, an internal gate forces
CE
OUT
high, independent of
CE
IN
.
CE
OUT
typically drives the CE, CS or Write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
CC
is at an in-
valid level.
ADM8697
LL
IN
LOW = 0
LL
IN
OK = 1
CE
IN
CE
OUT
Figure 5. Chip Enable Gating
t
1
= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
V2 V2
V1
V1
LL
IN
LOW LINE
RESET
CE
OUT
t
1
t
1
CE
IN
Figure 6. Chip Enable Timing
Power Fail Warning Comparator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output (
PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio
REV. A
ADM8696/ADM8697–Typical Performance Curves
–8–
53
49
20 120
52
50
40
51
1008060
V
CC
= +5V
TEMPERATURE –
°
C
RESET ACTIVE TIME – ms
Figure 11. RESET Active Time vs. Temperature
10
90
100
0%
A4 3.36 V
500ms
1V
1V
Figure 12.
RESET
Output Voltage vs. Supply Voltage
5.5
3.0
2.0
10 100 100001000
4.5
2.5
3.5
4.0
5.0
TIME DELAY – ms
V
CC
– Volts
T
A
= +25°C
Figure 13.
RESET
Timeout Delay vs. V
CC
I
OUT
– mA
V
OUT
– Volts
5
4.94
10 10020 30 40 50 60 70 80 90
4.99
4.98
4.97
4.96
4.95
Figure 8. V
OUT
vs. I
OUT
Normal Operation
I
OUT
– µA
2.8
2.786
150 1050250 350 450 550 650 750 850 950
2.798
2.794
2.792
2.79
2.788
2.796
V
OUT
– Volts
Figure 9. V
OUT
vs. I
OUT
Battery Backup
1.29
20 120
1.32
1.30
40
1.31
1008060
PFI INPUT THRESHOLD – V
TEMPERATURE –
°
C
Figure 10. PFI Input Threshold vs. Temperature
REV. A
ADM8696/ADM8697
–9–
APPLICATIONS INFORMATION
Increasing the Drive Current (ADM8696)
If the continuous output current requirements at V
OUT
exceeds
100 mA or if a lower V
CC
–V
OUT
voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM8696)
can directly drive the base of the external transistor.
BATTERY
+5V
INPUT
POWER
0.1µF
PNP
TRANSISTOR
0.1µF
V
OUT
V
CC
BATT
ON
V
BATT
ADM8696
Figure 14. Increasing the Drive Current
Using a Rechargeable Battery for Backup (ADM8696)
If a capacitor or a rechargeable battery is used for backup, the
charging resistor should be connected to V
OUT
since this elimi-
nates the discharge path that would exist during power-down if
the resistor is connected to V
CC
.
V
OUT
V
CC
RECHARGABLE
BATTERY
+5V
INPUT
POWER
0.1µF
0.1µF
V
BATT
ADM8696
R
R
V
OUT
– V
BATT
I =
Figure 15. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added by connecting a resistor be-
tween the PFO output and the PFI input as shown in Fig-
ure 16. When PFO is low, resistor R3 sinks current from the
summing junction at the PFI pin. When PFO is high, the series
combination of R3 and R4 source current into the PFI summing
junction. This results in differing trip levels for the comparator.
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a three-state buffer (Figure
17a). When three-stated, the WDI input will float, thereby dis-
abling the watchdog timer.
This circuit is not entirely foolproof and it is possible a software
fault could erroneously three-state the buffer. This would pre-
vent the ADM869x from detecting that the microprocessor is no
longer operating correctly. In most cases, a better method is to
ADM869x
R2
1.3V
R1
PFO
7805
R4
R3
+7V TO +15V
INPUT
POWER
+5V
PFI
V
CC
TO
µP NMI
V
H
= 1.3V (1+ ––– + ––– )
V
L
= 1.3V (1+ ––– – ––––––––––––– )
ASSUMING R
4
< < R
3
THEN
HYSTERESIS V
H
– V
L
= 5V (––– )
R
1
R
2
R
1
R
3
R
1
R
2
R
1
R
2
R
1
(5V – 1.3V)
1.3V (R
3 +
R
4
)
Figure 16. Adding Hysteresis to the Power Fail Comparator
extend the watchdog period rather than disabling the watchdog.
This may be done under program control using the circuit
shown in Figure 17b. When the control input is high, the OSC
SEL pin is low and the watchdog timeout is set by the external
capacitor. A 0.01 µF capacitor sets a watchdog timeout delay of
100 s. When the control input is low, the OSC SEL pin is
driven high, selecting the internal oscillator. The 100 ms or the
1.6 s period is chosen, depending on which diode in Fig-
ure 17b is used. With D1 inserted, the internal timeout is set at
100 ms while with D2 inserted the timeout is set at 1.6 s.
WDI
ADM869x
WATCHDOG
STROBE
CONTROL
INPUT
Figure 17a. Programming the Watchdog Input
OSC IN
OSC SEL
ADM869x
CONTROL
INPUT*
D1 D2
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 17b. Programming the Watchdog Input
REV. A
P1-P3P4-P6P7-P9P10-P12P13-P13

ADM8697ARW

Mfr. #:
Buy ADM8697ARW
Manufacturer:
Analog Devices / Linear Technology
Description:
Supervisory Circuits IMPROVED ADM697 I.C
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet