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MC75174BPG

P1-P3P4-P6P7-P9P10-P12P13-P13
MC75172B, MC75174B
http://onsemi.com
10
Termination Resistors
Transmission line theory states that, in order to preserve
the shape and integrity of a waveform traveling along a
cable, the cable must be terminated in an impedance equal
to its characteristic impedance. In a system such as that
depicted in Figure 18, in which data can travel in both
directions, both physical ends of the cable must be
terminated. Stubs, leading to each receiver and driver,
should be as short as possible.
Leaving off the terminations will generally result in
reflections which can have amplitudes of several volts
above V
CC
or below ground. These overshoots and
undershoots can disrupt the driver and/or receiver
operation, create false data, and in some cases damage
components on the bus.
Figure 18. Typical EIA−485 System
NOTES: 1.Terminating resistors R
T
must be located at the physical ends of the cable.
2.Stubs should be as short as possible.
3.Circuit ground of all drivers and receivers must be connected via a dedicated wire within the cable.
Do not rely on chassis ground or power line ground.
#8
TTL
R
TTL
TTL
#3
TTL
R
En
#2
TTL
TTL
En
TTL
R
TTL
#1
R
TTL
R
T
#1
En
D
#3
D
#5
D
TTL
En
#6
R
TTL
R
En
#5
R
#6
D
#7
R
T
TTL TTL
R
En
TTL
#4
D
5 “off” drivers (@ 0.06 U.L. each),
+8 receivers (@ 1.0 U.L. each) = 8.3 Unit Loads
R
T
= 120 W at each end of the cable.
#4
D
#2
120 W
Twisted
Pair
MC75172B, MC75174B
http://onsemi.com
11
COMPARING SYSTEM REQUIREMENTS
Characteristic Symbol EIA−485 EIA−422−A V.11 and X.27
GENERATOR (Driver)
Output Impedance (Note 1) Z
out
Not Specified t 100 W 50 10 100 W
Open Circuit Voltage
Differential
Single−Ended
V
OCD
V
OCS
1.5 to 6.0 V
t6.0 V
p6.0 V
p6.0 V
p6.0 V, w/3.9 kW, Load
p6.0 V, w/3.9 kW, Load
Loaded Differential Voltage V
OD
1.5 to 5.0 V, w/54 W load q 2.0 V or q 0.5 V
OCD
,
w/100 W load
q2.0 V or q 0.5 V
OCD
,
w/100 W load
Differential Voltage Balance DV
OD
t200 mV p400 mV t 400 mV
Output Common Mode Range V
CM
−7.0 to +12 V Not Specified Not Specified
Offset Voltage V
OS
−1.0 t V
OS
t 3.0 V p 3.0 V p3.0 V
Offset Voltage Balance DV
OS
t200 mV p400 mV t 400 mV
Short Circuit Current I
OS
p250 mA for −7.0 to 12 V p150 mA to ground p150 mA to ground
Leakage Current (V
CC
= 0) I
OLK
Not Specified p100 mA to −0.25 V thru
6.0 V
p100 mA to ± 0.25 V
Output Rise/Fall Time (Note 2) t
r
, t
f
p0.3 T
B
, w/54 W/1150 pF
load
p0.1 T
B
or p 20 ns, w/100
W load
p0.1 T
B
or p 20 ns, w/100
W load
RECEIVER
Input Sensitivity V
th
± 200 mV ± 200 mV ± 300 mV
Input Bias Voltage V
bias
p3.0 V p 3.0 V p3.0 V
Input Common Mode Range V
cm
−7.0 to 12 V −7.0 to 7.0 V −7.0 to 7.0 V
Dynamic Input Impedance R
in
Spec number of U.L. q4 kW q4 kW
NOTES: 1. Compliance with V.11 and X.27 (Blue book) output impedance requires external resistors in series with the outputs of the
MC75172B and MC75174B.
2. T
B
= Bit time.
Additional Information
Copies of the EIA Recommendations (EIA−485 and EIA−422−A) can be obtained from the Electronics Industries
Association, Washington, D.C. (202−457−4966). Copies of the CCITT Recommendations (V.11 and X.27) can be obtained
from the United States Department of Commerce, Springfield, VA (703−487−4600).
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping
†
MC75172BDW
T
A
= −40° to +85°C
SOIC−20WB
38 Units / Rail
MC75172BDWG SOIC−20WB
(Pb−Free)
MC75172BDWR2 SOIC−20WB
1000 / Tape & Reel
MC75172BDWR2G SOIC−20WB
(Pb−Free)
MC75174BDW SOIC−20WB
38 Units / Rail
MC75174BDWG SOIC−20WB
(Pb−Free)
MC75174BDWR2 SOIC−20WB
1000 / Tape & Reel
MC75174BDWR2G SOIC−20WB
(Pb−Free)
MC75174BP PDIP−16
25 Units / Rail
MC75174BPG PDIP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC75172B, MC75174B
http://onsemi.com
12
PACKAGE DIMENSIONS
SOIC−20 WB
DW SUFFIX
PLASTIC PACKAGE
CASE 751D−05
ISSUE G
20
1
11
10
B20X
H10X
C
L
18X
A1
A
SEATING
PLANE
q
h X 45
_
E
D
M
0.25
M
B
M
0.25
S
A
S
B
T
e
T
B
A
DIM MIN MAX
MILLIMETERS
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q 0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
__
PDIP−16
P SUFFIX
PLASTIC PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
P1-P3P4-P6P7-P9P10-P12P13-P13

MC75174BPG

Mfr. #:
Buy MC75174BPG
Manufacturer:
ON Semiconductor
Description:
RS-485 Interface IC Quad EIA-485 Line Driver w/3 State Out
Lifecycle:
New from this manufacturer.
Delivery:
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