1
®
FN8121.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X4283, X4285
128K, 16K x 8 Bit
CPU Supervisor with 128K EEPROM
FEATURES
Selectable watchdog timer
•Low V
CC
detection and reset assertion
Four standard reset threshold voltages
Adjust low V
CC
reset threshold voltage using
special programming sequence
Reset signal valid to V
CC
= 1V
Low power CMOS
<20µA max standby current, watchdog on
<1µA standby current, watchdog OFF
3mA active current
128Kbits of EEPROM
64 byte page write mode
Self-timed write cycle
5ms write cycle time (typical)
Built-in inadvertent write protection
Power-up/power-down protection circuitry
Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lock
protection
400kHz 2-wire interface
2.7V to 5.5V power supply operation
Available packages
8 Ld SOIC
8 Ld TSSOP
Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X4283, X4285 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET
/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET
/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when V
CC
falls below the set minimum V
CC
trip point. RESET/RESET is asserted until V
CC
returns
to proper operating level and stabilizes. Four industry
standard Vtrip thresholds are available, however, Inter-
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
Watchdog
Timer Reset
Data
Register
Command
Decode &
Control
Logic
SDA
SCL
V
CC
Reset &
Watchdog
Timebase
Power-on and
Generation
V
TRIP
+
-
RESET (X4283)
Reset
Low Voltage
Status
Register
Protect Logic
EEPROM Array
Watchdog Transition
Detector
WP
V
CC
Threshold
Reset logic
Block Lock Control
8Kb 4Kb 4Kb
RESET (X4285)
S0
S1
Kb=Kilobyte
Data Sheet May 23, 2006
2
FN8121.1
May 23, 2006
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as 64 bytes per page.
The device features an 2-wire interface and software
protocol allowing operation on an 2-wire bus.
PIN CONFIGURATION
PIN DESCRIPTION
S
1
V
SS
V
CC
SDA
SCL
3
2
4
1
6
7
5
8
S
0
WP
RST
/RST
V
CC
S
1
SCL
RST
/RST
V
SS
3
2
4
1
6
7
5
8
WP
SDA
S
0
8-Pin JEDEC SOIC
8-Pin TSSOP
Pin
(SOIC)
Pin
(TSSOP) Name Function
13 S
0
Device Select Input
24 S
1
Device Select Input
35RESET
/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
CC
falls below the minimum V
CC
sense level. It will remain ac-
tive until V
CC
rises above the minimum V
CC
sense level for 250ms. RESET/RESET
goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW
longer than the selectable Watchdog time out period. A falling edge on SDA, while
SCL is HIGH, resets the Watchdog Timer. RESET
/RESET goes active on power-up
and remains active for 250ms after the power supply stabilizes.
46 V
SS
Ground
57 SDASerial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is al-
ways active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET
/RESET going active.
68 SCLSerial Clock. The Serial Clock controls the serial bus timing for data input and output.
71 WPWrite Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the
control register.
82 V
CC
Supply Voltage
X4283, X4285
3
FN8121.1
May 23, 2006
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
V
CC
RANGE
(V)
V
TRIP
RANGE
(V)
TEMP
RANGE (°C) PACKAGE
PKG.
DWG #
X4283S8-2.7 X4283 F X4285S8-2.7 X4285 F 2.7 to 5.5 2.55 to 2.7 0 to 70 8 Ld SOIC
(150 mil)
MDP0027
X4283S8Z-2.7 (Note) X4283 ZF X4285S8Z-2.7
(Note)
X4285 ZF 0 to 70 8 Ld SOIC
(150 mil) (Pb-free)
MDP0027
X4283S8I-2.7 X4283 G X4285S8I-2.7 X4285 G -40 to +85 8 Ld SOIC
(150 mil)
MDP0027
X4283S8IZ-2.7
(Note)
X4283 ZG X4285S8IZ-2.7
(Note)
X4285 ZG -40 to +85 8 Ld SOIC
(150 mil) (Pb-free)
MDP0027
X4283V8-2.7 4283 F X4285V8-2.7 4285 F 0 to 70 8 Ld TSSOP
(4.4mm)
M8.173
X4283V8Z-2.7 (Note) 4283 FZ X4285V8Z-2.7
(Note)
4285 FZ 0 to 70 8 Ld TSSOP
(4.4mm) (Pb-free)
M8.173
X4283V8I-2.7 4283 G X4285V8I-2.7 4285 G -40 to +85 8 Ld TSSOP
(4.4mm)
M8.173
X4283V8IZ-2.7
(Note)
4283 GZ X4285V8IZ-2.7
(Note)
4285 GZ -40 to +85 8 Ld TSSOP
(4.4mm) (Pb-free)
M8.173
X4283S8-2.7A* X4283 AN X4285S8-2.7A X4285 AN 2.85 to 3.0 0 to 70 8 Ld SOIC
(150 mil)
MDP0027
X4283S8Z-2.7A
(Note)
X4283 ZAN X4285S8Z-2.7A
(Note)
X4285 ZAN 0 to 70 8 Ld SOIC
(150 mil) (Pb-free)
MDP0027
X4283S8I-2.7A* X4283 AP X4285S8I-2.7A X4285 AP -40 to +85 8 Ld SOIC
(150 mil)
MDP0027
X4283S8IZ-2.7A*
(Note)
X4283 ZAP X4285S8IZ-2.7A
(Note)
X4285 ZAP -40 to +85 8 Ld SOIC
(150 mil) (Pb-free)
MDP0027
X4283V8-2.7A 4283 AN X4285V8-2.7A 4285 AN 0 to 70 8 Ld TSSOP
(4.4mm)
M8.173
X4283V8Z-2.7A
(Note)
4283 ANZ X4285V8Z-2.7A
(Note)
4285 ANZ 0 to 70 8 Ld TSSOP
(4.4mm) (Pb-free)
M8.173
X4283V8I-2.7A 4283 AP X4285V8I-2.7A 4285 AP -40 to +85 8 Ld TSSOP
(4.4mm)
M8.173
X4283V8IZ-2.7A
(Note)
4283 APZ X4285V8IZ-2.7A
(Note)
4285 APZ -40 to +85 8 Ld TSSOP
(4.4mm) (Pb-free)
M8.173
X4283S8 X4283 X4285S8 X4285 4.5 to 5.5 4.5 to 4.75 0 to 70 8 Ld SOIC
(150 mil)
MDP0027
X4283S8Z (Note) X4283 Z X4285S8Z (Note) X4285 Z 0 to 70 8 Ld SOIC
(150 mil) (Pb-free)
MDP0027
X4283S8I X4283 I X4285S8I X4285 I -40 to +85 8 Ld SOIC
(150 mil)
MDP0027
X4283S8IZ (Note) X4283 ZI X4285S8IZ (Note) X4285 ZI -40 to +85 8 Ld SOIC
(150 mil) (Pb-free)
MDP0027
X4283V8 4283 X4285V8 4285 0 to 70 8 Ld TSSOP
(4.4mm)
M8.173
X4283V8Z (Note) 4283 Z X4285V8Z (Note) 4285 Z 0 to 70 8 Ld TSSOP
(4.4mm) (Pb-free)
M8.173
X4283V8I 4283 I X4285V8I 4285 I -40 to +85 8 Ld TSSOP
(4.4mm)
M8.173
X4283, X4285

X4283V8-4.5A

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC SUPERVISOR CPU 128K EE 8TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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