74VHCT373A
4/13
Table 6: DC Specifications
Table 7: AC Electrical Characteristics (Input t
r
= t
f
= 3ns)
(*) Voltage range is 5.0V ± 0.5V
Note 1: Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
IH
High Level Input
Voltage
4.5 to
5.5
222V
V
IL
Low Level Input
Voltage
4.5 to
5.5
0.8 0.8 0.8 V
V
OH
High Level Output
Voltage
4.5
I
O
=-50 µA
4.4 4.5 4.4 4.4
V
4.5
I
O
=-8 mA
3.94 3.8 3.7
V
OL
Low Level Output
Voltage
4.5
I
O
=50 µA
0.0 0.1 0.1 0.1
V
4.5
I
O
=8 mA
0.36 0.44 0.55
I
OZ
High Impedance
Output Leakage
Current
4.5 to
5.5
V
I
= V
IH
or V
IL
V
O
= 0V to 5.5
±0.25 ± 2.5 ± 2.5 µA
I
I
Input Leakage
Current
0 to
5.5
V
I
= 5.5V or GND
± 0.1 ± 1.0 ± 1.0 µA
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
44040µA
+I
CC
Additional Worst
Case Supply
Current
5.5
One Input at 3.4V,
other input at V
CC
or GND
1.35 1.5 1.5 mA
I
OPD
Output Leakage
Current
0
V
OUT
= 5.5V
0.5 5.0 5.0 µA
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
t
PLH
t
PHL
Propagation Delay
Time
LE to Q
5.0
(*)
15 5.4 12.3 1.0 13.5 1.0 13.5
ns
5.0
(*)
50 6.0 13.3 1.0 14.5 1.0 14.5
t
PLH
t
PHL
Propagation Delay
Time
D to Q
5.0
(*)
15 6.4 8.5 1.0 9.5 1.0 9.5
ns
5.0
(*)
50 7.1 9.5 1.0 10.5 1.0 10.5
t
PZL
t
PZH
Output Enable
Time
5.0
(*)
15
RL = 1K
6.2 10.9 1.0 12.5 1.0 12.5
ns
5.0
(*)
50 6.9 11.9 1.0 13.5 1.0 13.5
t
PLZ
t
PHZ
Output Disable
Time
5.0
(*)
50 RL = 1K 6.7 11.2 1.0 12.0 1.0 12.0 ns
t
w
Pulse Width (LE)
HIGH
5.0
(*)
6.5 8.5 8.5 ns
t
s
Setup Time D to LE
HIGH or LOW
5.0
(*)
1.5 1.5 1.5 ns
t
h
Hold Time D to LE
HIGH or LOW
5.0
(*)
3.5 3.5 3.5 ns
t
OSLH
t
OSHL
Output to Output
Skew time (note 1)
5.0
(*)
50 1.0 1.0 1.0 ns
74VHCT373A
5/13
Table 8: Capacitive Characteristics
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per Latch)
Table 9: Dynamic Switching Characteristics
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Symbol Parameter
Test Condition Value
Unit
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
C
IN
Input Capacitance
410 10 10pF
C
OUT
Output
Capacitance
9pF
C
PD
Power Dissipation
Capacitance
(note 1)
14 pF
Symbol Parameter
Test Condition Value
Unit
V
CC
(V)
T
A
= 25°C
-40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
V
OLP
Dynamic Low
Voltage Quiet
Output (note 1, 2)
5.0
C
L
= 50 pF
0.6 0.9
V
V
OLV
-0.9 -0.6
V
IHD
Dynamic High
Voltage Input
(note 1, 3)
5.0 2.0
V
ILD
Dynamic Low
Voltage Input
(note 1, 3)
5.0 0.8
74VHCT373A
6/13
Figure 4: Test Circuit
C
L
=15/50pF or equivalent (includes jig and probe capacitance)
R
L
= R1 = 1Kor equivalent
R
T
= Z
OUT
of pulse generator (typically 50)
Figure 5: Waveform - LE To Qn Propagation Delays, LE Minimun Pulse Width, Dn To LE Setup
And Hold Times (f=1MHz; 50% duty cycle)
TEST SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
CC
t
PZH
, t
PHZ
GND

74VHCT373AMTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Latches Octal "D" Latch
Lifecycle:
New from this manufacturer.
Delivery:
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