LTC2609/LTC2619/LTC2629
4
26091929fb
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T
A
= 25°C.
REFA = REFB = REFC = REFD = 4.096V (V
CC
= 5V), REFA = REFB = REFC = REFD = 2.048V (V
CC
= 2.7V). REFLO = 0V, V
OUT
= unloaded,
unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
AC Performance
t
S
Settling Time (Note 5) ±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7 7
9
7
9
10
µs
µs
µs
Settling Time for 1LSB Step
(Note 6)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7 2.7
4.8
2.7
4.8
5.2
µs
µs
µs
Voltage Output Slew Rate 0.7 0.7 0.7 V/µs
Capacitive Load Driving 1000 1000 1000 pF
Glitch Impulse At Mid-Scale Transition 12 12 12 nV • s
Multiplying Bandwidth 180 180 180 kHz
e
n
Output Voltage Noise Density At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µV
P-P
Digital I/O (Note 9)
V
IL
Low Level Input Voltage
(SDA and SCL)
l
0.3V
CC
V
V
IH
High Level Input Voltage
(SDA and SCL)
l
0.7V
CC
V
V
IL(CAn)
Low Level Input Voltage on CAn
(n = 0, 1, 2)
See Test Circuit 1
l
0.15V
CC
V
V
IH(CAn)
High Level Input Voltage on CAn
(n = 0, 1, 2)
See Test Circuit 1
l
0.85V
CC
V
R
INH
Resistance from CAn (n = 0, 1, 2)
to V
CC
to Set CAn = V
CC
See Test Circuit 2
l
10
R
INL
Resistance from CAn (n = 0, 1, 2)
to GND to Set CAn = GND
See Test Circuit 2
l
10
R
INF
Resistance from CAn (n = 0, 1, 2)
to V
CC
or GND to Set CAn = Float
See Test Circuit 2
l
2
V
OL
Low Level Output Voltage Sink Current = 3mA
l
0 0.4 V
t
OF
Output Fall Time V
O
= V
IH(MIN)
to V
O
= V
IL(MAX)
,
C
B
= 10pF to 400pF (Note 7)
l
20 + 0.1C
B
250 ns
t
SP
Pulse Width of Spikes Suppressed by
Input Filter
l
0 50 ns
I
IN
Input Leakage 0.1V
CC
≤ V
IN
≤ 0.9V
CC
l
1 µA
C
IN
I/O Pin Capacitance (Note 12)
l
10 pF
C
B
Capacitive Load for Each Bus Line
l
400 pF
C
CAX
External Capacitive Load on Address
Pins CAn (n = 0, 1, 2)
l
10 pF
electrical characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. REFA = REFB = REFC = REFD = 4.096V (V
CC
= 5V), REFA = REFB =
REFC = REFD = 2.048V (V
CC
= 2.7V). REFLO = 0V, V
OUT
= unloaded, unless otherwise noted. (Note 9)
LTC2609/LTC2619/LTC2629
5
26091929fb
timing characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (See Figure 1) (Notes 8, 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
= 2.7V to 5.5V
f
SCL
SCL Clock Frequency
l
0 400 kHz
t
HD(STA)
Hold Time (Repeated) Start Condition
l
0.6 µs
t
LOW
Low Period of the SCL Clock Pin
l
1.3 µs
t
HIGH
High Period of the SCL Clock Pin
l
0.6 µs
t
SU(STA)
Set-Up Time for a Repeated Start Condition
l
0.6 µs
t
HD(DAT)
Data Hold Time
l
0 0.9 µs
t
SU(DAT)
Data Set-Up Time
l
100 ns
t
r
Rise Time of Both SDA and SCL Signals (Note 7)
l
20 + 0.1C
B
300 ns
t
f
Fall Time of Both SDA and SCL Signals (Note 7)
l
20 + 0.1C
B
300 ns
t
SU(STO)
Set-Up Time for Stop Condition
l
0.6 µs
t
BUF
Bus Free Time Between a Stop and Start Condition
l
1.3 µs
t
1
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
l
400 ns
t
2
LDAC Low Pulse Width
l
20 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code k
L
to code
2
N
– 1, where N is the resolution and k
L
is given by k
L
= 0.016(2
N
/V
REF
),
rounded to the nearest whole code. For V
REF
= 4.096V and N = 16, k
L
=
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL at 0V or V
CC
, CA0, CA1 and CA2 floating.
Note 4: Inferred from measurement at code kL (see Note 2) and at full-Scale.
Note 5: V
CC
= 5V, V
REF
= 4.096V. DAC is stepped 1/4 scale to 3/4 scale and
3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 6: V
CC
= 5V, V
REF
= 4.096V. DAC is stepped ±1LSB between half scale
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 7: C
B
= capacitance of one bus line in pF.
Note 8: All values refer to V
IH(MIN)
and V
IL(MAX)
levels.
Note 9: These specifications apply to LTC2609/LTC2609-1,
LTC2619/LTC2619-1, LTC2629/LTC2629-1.
Note 10: DC crosstalk is measured with V
CC
= 5V, REFA = REFB = REFC
= REFD = 4.096V, with the measured DAC at mid-scale, unless otherwise
noted.
Note 11: R
L
= 2kΩ to GND or V
CC
.
Note 12: Guaranteed by design and not production tested.
LTC2609/LTC2619/LTC2629
6
26091929fb
typical perFormance characteristics
DNL vs Temperature INL vs V
REF
DNL vs V
REF
Settling to ±1LSB Settling of Full-Scale Step
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature
LTC2609
CODE
0 16384 32768 49152 65535
INL (LSB)
2609 G01
32
24
16
8
0
–8
–16
–24
–32
V
CC
= 5V
V
REF
= 4.096V
CODE
0 16384 32768 49152 65535
DNL (LSB)
2609 G02
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
CC
= 5V
V
REF
= 4.096V
TEMPERATURE (°C)
–50
–30 –10 10 30 50 70 90
INL (LSB)
2609 G03
32
24
16
8
0
–8
–16
–24
–32
V
CC
= 5V
V
REF
= 4.096V
INL (POS)
INL (NEG)
TEMPERATURE (°C)
–50
–30 –10 10 30 50 70 90
DNL (LSB)
2609 G04
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
V
CC
= 5V
V
REF
= 4.096V
DNL (POS)
DNL (NEG)
2µs/DIV
2609 G07
V
OUT
100µV/DIV
SCL
2V/DIV
V
CC
= 5V, V
REF
= 4.096V
1/4 SCALE TO 3/4 SCALE STEP
R
L
= 2k, C
L
= 200pF
AVERAGE OF 2048 EVENTS
9.7µs
9TH CLOCK
OF 3RD DATA
BYTE
5µs/DIV
2609 G08
V
OUT
100µV/DIV
SCR
2V/DIV
SETTLING TO ±1LSB
V
CC
= 5V, V
REF
= 4.096V
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
12.3µs
9TH CLOCK OF
3RD DATA BYTE

LTC2609IGN-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Quad 16-bit I2C Voltage Output DAC
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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