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LTC2619IGN-1#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LTC2609/LTC2619/LTC2629
13
26091929fb
test circuits
timing Diagram
100Ω
R
INH
/R
INL
/R
INF
V
IH(CAn)
/V
IL(CAn)
CAn
GND
2609 TC
V
DD
Test Circuit 2Test Circuit 1
CAn
SDA
t
f
S
t
r
t
LOW
t
HD(STA)
ALL VOLTAGE LEVELS REFER TO V
IH(MIN)
AND V
IL(MAX)
LEVELS
t
HD(DAT)
t
SU(DAT)
t
SU(STA)
t
HD(STA)
t
SU(STO)
t
SP
t
BUF
t
r
t
f
t
HIGH
SCL
S P S
2609 F01
Figure 1
LTC2609/LTC2619/LTC2629
14
26091929fb
operation
Power-On Reset
The LTC2609/LTC2619/LTC2629 clear the outputs to
zero-scale when power is first applied, making system
initialization consistent and repeatable. The LTC2609-1/
L
TC2619-1/LTC2629-1 set the voltage outputs to mid-scale
when power is first applied.
For some applications, downstream circuits are active dur-
ing DAC power-up and may be sensitive to nonzero outputs
from the DAC during this time. The LTC2609/LTC2619/
LTC2629 contain circuitry to reduce the power-on glitch;
furthermore, the glitch amplitude can be made arbitrarily
small by reducing the ramp rate of the power supply. For
example, if the power supply is ramped to 5V in 1ms, the
analog outputs rise less than 10mV above ground (typ)
during power-on. See Power-On Reset Glitch in the Typical
Performance Characteristics section.
Power Supply Sequencing
The voltage at REFx (Pins 3, 6, 12 and 15) should be kept
within the range –0.3V ≤ REFx ≤ V
CC
+ 0.3V (see Absolute
Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at V
CC
(Pin 16) is
in transition. The REFx pins can be clamped to stay below
the maximum voltage by using Schottky diodes as shown
in Figure 2, thereby easing sequencing constraints.
LTC2609/
LTC2619/
LTC2629
V
CC
16
3
6
12
15
2609 F02
V
CC
REFA
REFB
REFC
REFD
REFA
REFB
REFC
REFD
Figure 2. Use of Schottky Diodes for Power Supply Sequencing
Transfer Function
The digital-to-analog transfer function is:
V
k
REFx REFLO REFLO
OUT IDEAL
N
( )
[ – ]=
+
2
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REFx is the voltage at REFA,
REFB, REFC and REFD (Pins 3, 6, 12 and 15).
Serial Digital Interface
The LTC2609/LTC2619/LTC2629 communicate with a host
using the standard 2-wire I
2
C interface. The Timing Diagram
(Figure 1) shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The value of
these pull-up resistors is dependent on the power supply and
can be obtained from the I
2
C specifications. For an I
2
C bus
operating in the fast mode, an active pull-up will be necessary
if the bus capacitance is greater than 200pF. The V
CC
power
should not be removed from the LTC2609/LTC2619/LTC2629
when the I
2
C bus is active to avoid loading the I
2
C bus lines
through the internal ESD protection diodes.
The LTC2609/LTC2619/LTC2629 are receive-only (slave)
devices. The master can write to the LTC2609/LTC2619/
LTC2629. The LTC2609/LTC2619/LTC2629 do not respond
to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be high.
A bus master signals the beginning of a communication
to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I
2
C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the
latest byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge clock
pulse. The slave-receiver must pull down the SDA bus line
LTC2609/LTC2619/LTC2629
15
26091929fb
operation
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse.
The LTC2609/LTC2619/LTC2629 respond to a write by a
master in this manner. The LTC2609/LTC2619/LTC2629
do not acknowledge a read (retains SDA HIGH during the
period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: V
CC
, GND or float. This results
in 27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
In addition to the address selected by the address pins,
the parts also respond to a global address. This address
allows a common write to all LTC2609, LTC2619 and
LTC2629 parts to be accomplished with one 3-byte write
transaction on the I
2
C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins (CA0,
CA1 and CA2) is 10pF, as these pins are driven during
address detection to determine if they are floating.
Write Word Protocol
The master initiates communication with the LTC2609/
LTC2619/LTC2629 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2609/
LTC2619/LTC2629 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the
global address. The master then transmits three bytes of
data. The LTC2609/LTC2619/LTC2629 acknowledges each
byte of data by pulling the SDA line low at the 9th clock of
each data byte transmission. After receiving three complete
bytes of data, the LTC2609/LTC2619/LTC2629 executes the
command specified in the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2609/LTC2619/LTC2629 do not
acknowledge the extra bytes of data (SDA is high during
the 9th clock).
The format of the three data bytes is shown in Figure 3.
The first byte of the input word consists of the 4-bit com-
mand and 4-bit DAC address. The next two bytes consist
of the 16-bit data word. The 16-bit data word consists of
the 16-, 14- or 12-bit input code, MSB to LSB, followed by
0, 2 or 4 don’t care bits (LTC2609, LTC2619 and LTC2629
respectively). A typical LTC2609 write transaction is shown
in Figure 4.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 2. The first four commands in the table
consist of write and update operations. A write operation
Table 1. Slave Address Map
CA2 CA1 CA0 SA6 SA5 SA4 SA3 SA2 SA1 SA0
GND GND GND 0 0 1 0 0 0 0
GND GND FLOAT 0 0 1 0 0 0 1
GND GND V
CC
0 0 1 0 0 1 0
GND FLOAT GND 0 0 1 0 0 1 1
GND FLOAT FLOAT 0 1 0 0 0 0 0
GND FLOAT V
CC
0 1 0 0 0 0 1
GND V
CC
GND 0 1 0 0 0 1 0
GND V
CC
FLOAT 0 1 0 0 0 1 1
GND V
CC
V
CC
0 1 1 0 0 0 0
FLOAT GND GND 0 1 1 0 0 0 1
FLOAT GND FLOAT 0 1 1 0 0 1 0
FLOAT GND V
CC
0 1 1 0 0 1 1
FLOAT FLOAT GND 1 0 0 0 0 0 0
FLOAT FLOAT FLOAT 1 0 0 0 0 0 1
FLOAT FLOAT V
CC
1 0 0 0 0 1 0
FLOAT V
CC
GND 1 0 0 0 0 1 1
FLOAT V
CC
FLOAT 1 0 1 0 0 0 0
FLOAT V
CC
V
CC
1 0 1 0 0 0 1
V
CC
GND GND 1 0 1 0 0 1 0
V
CC
GND FLOAT 1 0 1 0 0 1 1
V
CC
GND V
CC
1 1 0 0 0 0 0
V
CC
FLOAT GND 1 1 0 0 0 0 1
V
CC
FLOAT FLOAT 1 1 0 0 0 1 0
V
CC
FLOAT V
CC
1 1 0 0 0 1 1
V
CC
V
CC
GND 1 1 1 0 0 0 0
V
CC
V
CC
FLOAT 1 1 1 0 0 0 1
V
CC
V
CC
V
CC
1 1 1 0 0 1 0
GLOBAL ADDRESS 1 1 1 0 0 1 1
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LTC2619IGN-1#PBF

Mfr. #:
Buy LTC2619IGN-1#PBF
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Quad 14-bit I2C Voltage Output DAC
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New from this manufacturer.
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