MAX9235
10-Bit LVDS Serializer
_______________________________________________________________________________________ 7
Detailed Description
The MAX9235 10-bit serializer transmits data over bal-
anced media that may be a standard twisted-pair cable
or PCB traces at 100Mbps to 450Mbps. The interface
may be single- or double-terminated point-to-point. A
double-terminated point-to-point interface uses a 100Ω-
termination resistor at each end of the interface, result-
ing in a 50Ω load. The serializer requires a deserializer
such as the MAX9206 for a complete data transmission
application.
A high-state start bit and a low-state stop bit, added
internally, frame the 10-bit parallel input data and
ensure a transition in the serial data stream. Therefore,
12 serial bits are transmitted for each 10-bit parallel
input. The MAX9235 accepts a 16MHz to 45MHz refer-
ence clock, producing a serial data rate of 192Mbps
(12 bits x 16MHz) to 540Mbps (12 bits x 45MHz). Since
only 10 bits are from input data, the actual throughput
is 10 times the TCLK frequency.
To transmit data, the serializer sequences through two
modes: initialization mode and data transmission mode.
Initialization Mode
When V
CC
is applied, the outputs are held in high
impedance and internal circuitry is disabled by on-chip
power-on-reset circuitry. When V
CC
reaches 2.35V, the
PLL starts to lock to a local reference clock. The refer-
ence clock, TCLK, is provided by the system. The seri-
alizer locks within 2049 cycles of TCLK. Once locked,
the serializer is ready to send data.
Data Transmission Mode
After initialization, input data at IN0–IN9 are clocked
into the serializer by the TCLK input. Data strobes on
the rising edge of TCLK.
A start bit high and a stop bit low frame the 10-bit data
and function as the embedded clock edge in the serial
data stream. The serial rate is the TCLK frequency
times the data and appended bits. For example, if
TCLK is 40MHz, the serial rate is 40 x 12 (10 + 2 bits) =
480Mbps. Since only 10 bits are from input data, the
payload rate is 40 x 10 = 400Mbps.
High-Impedance State
The serializer output pins (OUT+ and OUT-) are held in
high impedance when V
CC
is first applied and while the
PLL is locking to the local reference clock. If the serial-
izer goes into high impedance, the deserializer loses
PLL lock and needs to reestablish phase lock before
data transfer can resume. This is done by transmitting
all zeroes for at least one frame.
Applications Information
Power-Supply Bypassing
Bypass V
CC
with high-frequency surface-mount ceram-
ic 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smaller valued capaci-
tor closest to V
CC
.
Differential Traces and Termination
Use controlled-impedance media and terminate at both
ends of the transmission line in the media's characteris-
tic impedance. Termination with a single resistor at the
end of a point-to-point link typically provides acceptable
performance. The MAX9235 output levels are specified
for double-terminated point-to-point applications. With a
single 100Ω termination, the output swing is larger.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by a differential receiver.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
The differential output signals should be routed close to
each other to cancel their external magnetic field.
Maintain a constant distance between the differential
traces to avoid discontinuities in differential impedance.
Avoid 90° turns and minimize the number of vias to fur-
ther prevent impedance discontinuities.
