DC1525A-K Datasheet DC1525A-H, DC1525A-K, DC1525A-C | P1-P3

dc1525af

DEMO MANUAL DC1525A

DESCRIPTION

LTC2175-14/-12,

LTC2174-14/-12, LTC2173-14/-12, LTC2172-14/-12,

LTC2171-14/-12, LTC2170-14/-12

12-Bit/14-Bit, 25Msps to 125Msps Quad ADCs

Demonstration circuit 1525A supports a family of

14-Bit/12-Bit 25Msps to 125Msps ADCs. Each assem-

bly features one of the following devices: LTC

2175-14,

LTC2175-12, LTC2174-14, LTC2174-12, LTC2173-14,

LTC2173-12, LTC2172-14, LTC2172-12, LTC2171-14,

LTC2171-12, LTC2170-14, LTC2170-12 high speed,

quad ADCs.

The versions of the 1525A demo board are listed in Table1.

Depending on the required resolution and sample rate,

L, LT, LTC, LTM, μModule, Linear Technology and the Linear logo are registered trademarks

and QuikEval and PScope are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

the DC1525A is supplied with the appropriate ADC. The

circuitry on the analog inputs is optimized for analog input

frequencies from 5MHz to 140MHz. Refer to the data sheet

for proper input networks for different input frequencies.

Design files for this circuit board are available at

http://www.linear.com/demo

Table 1. DC1525A Variants

DC1525A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY

1525A-A LTC2175-14 14-Bit 125Msps 5MHz to 140MHz

1525A-B LTC2174-14 14-Bit 105Msps 5MHz to 140MHz

1525A-C LTC2173-14 14-Bit 80Msps 5MHz to 140MHz

1525A-D LTC2172-14 14-Bit 65Msps 5MHz to 140MHz

1525A-E LTC2171-14 14-Bit 40Msps 5MHz to 140MHz

1525A-F LTC2170-14 14-Bit 25Msps 5MHz to 140MHz

1525A-G LTC2175-12 12-Bit 125Msps 5MHz to 140MHz

1525A-H LTC2174-12 12-Bit 105Msps 5MHz to 140MHz

1525A-I LTC2173-12 12-Bit 80Msps 5MHz to 140MHz

1525A-J LTC2172-12 12-Bit 65Msps 5MHz to 140MHz

1525A-K LTC2171-12 12-Bit 40Msps 5MHz to 140MHz

1525A-L LTC2170-12 12-Bit 25Msps 5MHz to 140MHz

dc1525af

DEMO MANUAL DC1525A

QUICK START PROCEDURE

Demonstration circuit 1525A is easy to set up to evaluate

the performance of the LTC2175 A/D converters. Refer to

Figure 1 for proper measurement equipment setup and

follow this procedure.

Setup

If a DC1371 QuikEval™ II Data Acquisition and Collection

System was supplied with the DC1525A demonstration

circuit, follow the DC1371 Quick Start Guide to install the

required software and for connecting the DC1371 to the

DC1525A and to a PC.

DC1525A Demonstration Circuit Board Jumpers

The DC1525A demonstration circuit board should have

the following jumper settings as default positions: (as

per Figure 1).

J13: PAR/SER: Selects Parallel or Serial programming

mode. (Default – Serial)

Optional Jumpers:

J8: Term: Enables/Disable optional output termination.

(Default – Removed)

J5: ILVDS: Selects either 1.75mA or 3.5mA of output

current for the LVDS drivers. (Default – Removed)

J14: LANE: Selects either 1 lane or 2 lane output modes

(Default – Removed) NOTE: The DC1371 does not support

1 lane operation.

J15: SHDN: Enables and disables the LTC2175. (De-

fault–Removed)

J2: WP: Enable/Disables write protect for the EEPROM.

(Default – Removed)

Note: optional jumper should be left open to ensure proper

serial configuration.

Applying Power and Signals to the DC1525A

Demonstration Circuit

The DC1371 is used to acquire data from the DC1525A,

the DC1371 must FIRST be connected to a powered USB

port and have equal to 5V applied power BEFORE applying

3.6V to 6V across the pins marked V

and GND on the

DC1525A. DC1525A requires 3.6V for proper operation.

Regulators on the board produce the voltages required for

the ADC. The DC1525A demonstration circuit requires up

to 500mA depending on the sampling rate and the A/D

converter supplied.

The DC1525A should not be removed, or connected to

the DC1371 while power is applied.

PERFORMANCE SUMMARY

= 25°C)

PARAMETER CONDITION VALUE

Supply Voltage: DC1525A Depending on Sampling Rate and the A/D Converter Provided,

this Supply Must Provide Up to 500mA.

Optimized for 3V

[3V ↔ 6.0V Min/Max]

Analog Input Range Depending on SENSE Pin Voltage 1V

P-P

to 2V

P-P

Logic Input Voltages Minimum Logic High 1.3V

Maximum Logic Low 0.6V

Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode) 350mV/1.25V Common Mode

Minimum Logic Levels (100Ω Load, 3.5mA Mode) 247mV/1.25V Common Mode

Sampling Frequency (Convert Clock Frequency) See Table 1

Encode Clock Level Single-ended Encode Mode (ENC

–

Tied to GND) 0V to 3.6V

Encode Clock Level Differential Encode Mode (ENC

–

Not Tied to GND) 0.2V to 3.6V

Resolution See Table 1

Input Frequency Range See Table 1

SFDR See Applicable Data Sheet

SNR See Applicable Data Sheet

dc1525af

DEMO MANUAL DC1525A

QUICK START PROCEDURE

CHANNEL 4

dc1525a F01

CHANNEL 3

CHANNEL 2

PARALLEL/SERIAL

CHANNEL 1

ANALOG INPUTS

TO PROVIDED

POWER SUPPLY

USE PROVIDED

USB CABLE

3.5V

TO 6V

SINGLE-ENDED ENCODE CLOCK

USE PROVIDED DC1075

Figure 1. DC1525A Setup

Analog Input Network

For optimal distortion and noise performance the RC

network on the analog inputs may need to be optimized

for different analog input frequencies. For input frequen-

cies above 140MHz, refer to the LTC2175 data sheet for a

proper input network. Other input networks may be more

appropriate for input frequencies less that 5MHz.

In almost all cases, filters will be required on both analog

input and encode clock to provide data sheet SNR.

The filters should be located close to the inputs to avoid

reflections from impedance discontinuities at the driven

end of a long transmission line. Most filters do not present

50Ω outside the passband. In some cases, 3dB to 10dB

pads may be required to obtain low distortion.

If your generator cannot deliver full-scale signals without

distortion, you may benefit from a medium power amplifier

based on a Gallium Arsenide Gain block prior to the final

filter. This is particularly true at higher frequencies where

IC based operational amplifiers may be unable to deliver

the combination of low noise figure and High IP3 point

required. A high order filter can be used prior to this final

amplifier, and a relatively lower Q filter used between the

amplifier and the demo circuit.

Apply the analog input signal of interest to the SMA con-

nectors on the DC1525A demonstration circuit board

marked J3 AIN1, J4 AIN2, J6 AIN3, J7 AIN4. These inputs

correspond with channels 1 to 4 of the ADC respectively.

These inputs are capacitive coupled to Balun transform-

ers ETC1-1-13.

Encode Clock

NOTE: Apply an encode clock to the SMA connector on

the DC1525A demonstration circuit board marked J11

CLK+. As a default the DC1525A is populated to have a

single-ended input.

For the best noise performance, the ENCODE INPUT must

be driven with a very low jitter, square wave source. The

amplitude should be large, up to 3V

P-P

or 13dBm. When

P1-P3 P4-P6 P7-P9 P10-P10

DC1525A-K

Mfr. #:

Buy DC1525A-K

Manufacturer:

Analog Devices Inc.

Description:

Data Conversion IC Development Tools LTC2171-12 - 12-Bit, 40Msps, 1.8V Quad

Lifecycle:

New from this manufacturer.

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DC1525A-K

DC1525A-K

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