SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9449/D
Rev 1, 08/2002
1
Motorola, Inc. 2002
The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer
targeted for high performance clock tree applications. With output
frequencies up to 200 MHz and output skews less than 200 ps the device
meets the needs of the most demanding clock applications.
Features
15 LVCMOS compatible clock outputs
Two selectable LVCMOS and one differential LVPECL compatible clock
inputs
Selectable output frequency divider (divide-by-one and divide-by-two)
Maximum clock frequency of 200 MHz
Maximum clock skew of 200 ps
High-impedance output control
3.3V or 2.5V power supply
Drives up to 30 series terminated clock lines
Ambient temperature range –40°C to +85°C
52 lead LQFP packaging
Supports clock distribution in networking, telecommunication and
computing applications
Pin and function compatible to MPC949
Functional Description
The MPC9449 is specifically designed to distribute LVCMOS
compatible clock signals up to a frequency of 200 MHz. The device has
15 identical outputs, organized in 4 output banks. Each output bank
provides a retimed or frequency divided copy of the input signal with a
near zero skew. The output buffer supports driving of 50 terminated
transmission lines on the incident edge: each output is capable of driving
either one parallel terminated or two series terminated transmission lines.
Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In
addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input
reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the
OE control will force the outputs into high-impedance mode.
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a
2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The MPC9449 is pin and function compatible
but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
3.3V/2.5V 1:15
PECL/LVCMOS
CLOCK FANOUT BUFFER
MPC9449
MOTOROLA 2
Figure 1. MPC9449 Logic Diagram Figure 2. MPC9449 52–Lead Package Pinout (Top View)
NC
VCC
QB2
GND
QB1
VCC
QB0
GND
GND
QA1
VCC
QA0
GND
NC
VCC
QD4
GN
D
QD3
VCC
QD2
GN
D
QD1
VCC
QD0
GN
D
NC
NC
GND
QC0
VCC
QC1
GND
QC2
VCC
QC3
GND
GND
QD5
NC
CCLK_SEL
MR/OE
VCC
CCLK0
CCLK1
PCLK
PCLK
PCLK_SEL
DSELA
DSELB
DSELC
DSELD
GND
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
12345678910111213
39 38 37 36 35 34 33 32 31 30 29 28 27
26
MPC9449
÷2
÷1
V
CC
V
CC
CCLK0
CCLK1
PCLK
PCLK
PCLK_SEL
QA0
DSELB
DSELC
MR/OE
DSELD
DSELA
QA1
QB0
QB1
QB2
QC0
QC1
QC2
QC3
QD0
QD1
QD2
QD3
QD4
QD5
CCLK_SEL
0
1
0
1
0
1
0
1
0
1
0
1
Table 1: FUNCTION TABLE
Control Default 0 1
PCLK_SEL 0 LVCMOS clock input selected (CCLK0 or CCLK1) PCLK differential input selected
CCLK_SEL 0 CCLK0 selected CCLK1 selected
DSELA, DSELB,
DSELC, DSELD
0 0
0 0
÷1 ÷2
MR/OE 1 Outputs enabled Outputs disabled (high impedance)
Table 2: PIN CONFIGURATION
Pin I/O Type Function
PCLK, PCLK Input LVPECL Differential LVPECL clock input
CCLK0, CCLK1 Input LVCMOS LVCMOS clock inputs
PCLK_SEL Input LVCMOS LVPECL clock input select
CCLK_SEL Input LVCMOS LVCMOS clock input select
DSELA, DSELB, DSELC, DSELD Input LVCMOS Clock divider selection
MR/OE Input LVCMOS Output enable/disable (high-impedance tristate)
QA0-1, QB0-2, QC0-3, QD0-5 Output LVCMOS Clock outputs
GND Supply Ground Negative power supply (GND)
VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to
the positive power supply for correct operation
MPC9449
3 MOTOROLA
Table 3: GENERAL SPECIFICATIONS
Symbol Characteristics Min Typ Max Unit Condition
V
TT
Output Termination Voltage V
CC
2 V
MM ESD Protection (Machine Model) 200 V
HBM ESD Protection (Human Body Model) 2000 V
LU Latch–Up Immunity 200 mA
C
PD
Power Dissipation Capacitance 12 pF Per output
C
IN
Input Capacitance 4.0 pF Inputs
Table 4: ABSOLUTE MAXIMUM RATINGS
a
Symbol Characteristics Min Max Unit Condition
V
CC
Supply Voltage -0.3 3.8 V
V
IN
DC Input Voltage -0.3 V
CC
+0.3 V
V
OUT
DC Output Voltage -0.3 V
CC
+0.3 V
I
IN
DC Input Current ±20 mA
I
OUT
DC Output Current ±50 mA
T
S
Storage Temperature -65 125 °C
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.

MPC9449AE

Mfr. #:
Manufacturer:
Description:
Clock Buffer FSL 1-15 LVPECL/LVCM OS to LVCMOS Fanout
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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