ADC0808S250HW/C1:1 Datasheet ADC0808S250HW/C1:1, ADC0808S125/DB, ADC0808S125HW/C1:1 | P4-P6

Product data sheet Rev. 03 — 24 February 2009 4 of 23

NXP Semiconductors

ADC0808S125/250

Single 8-bit ADC, up to 125 MHz or 250 MHz

[1] See Table 3.

i.c. 15 - internally connected; leave open

OGND3 16 G data output ground 3

CCS 17 O complete conversion signal output

i.c. 18 - internally connected; leave open

CE_N 19 I(CMOS) chip enable input (active LOW)

IR 20 O(CMOS) in-range output

OTC 21 I(CMOS) control input for 2’s complement output

DGND1 22 G digital ground 1

CCD1(1V8)

23 P digital supply voltage 1 (1.8 V)

n.c. 24 - not connected

n.c. 25 - not connected

CCSSEL 26 I(CMOS) control input for CCS frequency selection

NC1V8 27 I not connected or connected to V

CCD1(1V8)

AGND1 28 G analog ground 1

CMADC 29 O regulator common-mode ADC output

FSIN/REFSEL 30 I full-scale reference voltage input/internal or external

reference selection

AGND2 31 G analog ground 2

INN 32 I complementary analog input

IN 33 I analog input

CCA1(3V3)

34 P analog supply voltage 1 (3.3 V)

i.c. 35 - internally connected; leave open

CLKSEL 36 I(CMOS) control input for clock input selection

CLK+ 37 I clock input

CLK− 38 I complementary clock input

DEL0 39 I(CMOS) complete conversion signal delay input 0

DEL1 40 I(CMOS) complete conversion signal delay input 1

D0 41 O data output bit 0

i.c. 42 - internally connected; leave open

CCO4(1V8)

43 P data output supply voltage 4 (1.8 V)

D1 44 O data output bit 1

i.c. 45 - internally connected; leave open

OGND4 46 G data output ground 4

D2 47 O data output bit 2

i.c. 48 - internally connected; leave open

DGND - G digital ground; exposed die pad

Table 2. Pin description

…continued

Symbol Pin Type

[1]

Description

Product data sheet Rev. 03 — 24 February 2009 5 of 23

NXP Semiconductors

ADC0808S125/250

Single 8-bit ADC, up to 125 MHz or 250 MHz

7. Functional description

7.1 CMOS/LVDS clock input

The circuit has two clock inputs CLK+ and CLK−, with two modes of operation:

• LVDS mode: CLK+ and CLK− inputs are at differential LVDS levels. An external

resistor of between 80 Ω and 120 Ω is required; see Figure 3.

• 1.8 V CMOS mode: CLK+ input is at 1.8 V CMOS level and sampling is done on the

rising edge of the clock input signal. In this case pin CLK− must be grounded;

see Figure 4.

Table 3. Pin type description

Type Description

I input

O output

I(CMOS) 1.8 V CMOS level input

O(CMOS) 1.8 V CMOS level output

P power supply

G ground

Fig 3. LVDS clock input

Fig 4. CMOS clock input

001aah720

LVDS

DRIVER

RECEIVER

gpd

O(dif)

undefined state

minimum V

idth

maximum V

idth

CLK+

CLK−

001aai272

CMOS

DRIVER

CLK−

CLK+

Product data sheet Rev. 03 — 24 February 2009 6 of 23

NXP Semiconductors

ADC0808S125/250

Single 8-bit ADC, up to 125 MHz or 250 MHz

7.2 Digital output coding

The digital outputs are 1.8 V CMOS compatible.

The data output format can be either binary or 2’s complement.

The in-range CMOS output pin IR will be HIGH during normal operation. When the ADC

input reaches either positive or negative full-scale, the IR output will be LOW.

Selection between output coding is controlled by pins OTC and CE_N.

[1] X = don’t care.

Table 4. Clock input format selection

Pin CLKSEL Clock input signal

Pins CLK+ and CLK−

HIGH or not connected LVDS

LOW 1.8 V CMOS

Table 5. Output coding with differential inputs

i(p-p)

= 2.0 V; V

ref(fs)

= 1.25 V; typical values to AGND.

Code Inputs (V) Output Outputs D7 to D0

i(IN)

i(INN)

Pin IR Binary 2’s complement

Underﬂow < 0.45 > 1.45 LOW 0000 0000 1000 0000

0 0.45 1.45 HIGH 0000 0000 1000 0000

1 - - HIGH 0000 0001 1000 0001

::: : : :

127 0.95 0.95 HIGH 0111 1111 1111 1111

::: : : :

254 - - HIGH 1111 1110 0111 1110

255 1.45 0.45 HIGH 1111 1111 0111 1111

Overﬂow > 1.45 < 0.45 LOW 1111 1111 0111 1111

Table 6. Output format selection

2’s complement outputs Chip enable Output data

Pin OTC Pin CE_N Pins D0 to D7, CCS and IR

LOW LOW active; binary

HIGH LOW active; 2’s complement

[1]

HIGH high-impedance

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

ADC0808S250HW/C1:1

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