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SC16C554IB80,551

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data Rev. 05 — 10 May 2004 34 of 55
9397 750 13132
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1] When using software flow control the Xon/Xoff characters cannot be used for data transfer.
5 EFR[5] Special Character Detect.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. The SC16C554/554D
compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to FIFO and ISR[4] will be
set to indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character. When this
feature is enabled, the normal software flow control must be disabled
(EFR[3-0] must be set to a logic 0).
4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], and
MCR[6] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new
values. This feature prevents existing software from altering or
overwriting the SC16C554/554D enhanced functions.
Logic 0 = Disable (normal default condition).
Logic 1 = Enable.
3:0 EFR[3:0] Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming
these bits. See Tabl e 22.
Table 22: Software flow control functions
[1]
Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls
0 0 X X No transmit flow control
1 0 X X Transmit Xon1/Xoff1
0 1 X X Transmit Xon2/Xoff2
1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1/Xoff1
X X 0 1 Receiver compares Xon2/Xoff2
1 0 1 1 Transmit Xon1/Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0 1 1 1 Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1 1 1 1 Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Table 21: Enhanced Feature Register bits description
…continued
Bit Symbol Description
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data Rev. 05 — 10 May 2004 35 of 55
9397 750 13132
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.11 SC16C554/554D external reset conditions
8. Limiting values
Table 23: Reset state for registers
Register Reset state
IER IER[7:0] = 0
ISR ISR[7:1] = 0; ISR[0] = 1
LCR LCR[7:0] = 0
MCR MCR[7:0] = 0
LSR LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR MSR[7:4] = input signals; MSR[3:0] = 0
FCR FCR[7:0] = 0
EFR EFR[7:0] = 0
Table 24: Reset state for outputs
Output Reset state
TXA, TXB, TXC, TXD HIGH
RTSA, RTSB, RTSC, RTSD HIGH
DTRA, DTRB, DTRC, DTRD HIGH
RXRDY HIGH
TXRDYLOW
Table 25: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage - 7 V
V
n
voltage at any pin GND − 0.3 V
CC
+ 0.3 V
T
amb
operating temperature −40 +85 °C
T
stg
storage temperature −65 +150 °C
P
tot(pack)
total power dissipation per
package
- 500 mW
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Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
9397 750 13132
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data Rev. 05 — 10 May 2004 36 of 55
9. Static characteristics
[1] Except x
2
, V
OL
= 1 V typical.
[2] When using crystal oscillator. The use of an external clock will increase the sleep current.
[3] Refer to Table 2 “Pin description” on page 9 for a listing of pins having internal pull-up resistors.
Table 26: DC electrical characteristics
T
amb
=
−
40
°
C to +85
°
C; V
CC
= 2.5 V, 3.3 V or 5.0 V
±
10%, unless otherwise specified.
Symbol Parameter Conditions 2.5 V 3.3 V 5.0 V Unit
Min Nom Max Min Nom Max Min Nom Max
V
IL(CK)
LOW-level clock input voltage −0.3 - 0.45 −0.3 - 0.6 −0.5 - 0.6 V
V
IH(CK)
HIGH-level clock input voltage 1.8 - V
CC
2.4 - V
CC
3.0 - V
CC
V
V
IL
LOW-level input voltage
(except X1 clock)
−0.3 - 0.65 −0.3 - 0.8 −0.5 - 0.8 V
V
IH
HIGH-level input voltage
(except X1 clock)
1.6 - - 2.0 - - 2.2 - - V
V
OL
LOW-level output voltage
on all outputs
[1]
I
OL
=5mA
(databus)
--------0.4V
I
OL
=4mA
(other outputs)
-----0.4---V
I
OL
=2mA
(databus)
--0.4------V
I
OL
= 1.6 mA
(other outputs)
--0.4------V
V
OH
HIGH-level output voltage I
OH
= −5mA
(databus)
------2.4--V
I
OH
= −1mA
(other outputs)
---2.0-----V
I
OH
= −800 µA
(data bus)
1.85 - - - - - - - - V
I
OH
= −400 µA
(other outputs)
1.85 - - - - - - - - V
I
LIL
LOW-level input leakage
current
--±10 - - ±10 - - ±10 µA
I
CL
clock leakage - - ±30 - - ±30 - - ±30 µA
I
CC
supply current f = 5 MHz - - 4.5 - - 6 - - 6 mA
I
CCsleep
sleep current
[2]
-1--1--1-mA
C
i
input capacitance - - 5 - - 5 - - 5 pF
R
pu(int)
internal pull-up resistance
[3]
500 - - 500 - - 500 - - kΩ
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P55

SC16C554IB80,551

Mfr. #:
Buy SC16C554IB80,551
Manufacturer:
NXP Semiconductors
Description:
IC UART QUAD W/FIFO 80-LQFP
Lifecycle:
New from this manufacturer.
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