ADM1186 Data Sheet
Rev. B | Page 14 of 28
If the output of the 2.5 V regulator meets the UV level when the
blanking time elapses, the state machine continues the power-up
sequence, moving into the DELAY 2 state. A time delay, set by
the capacitor connected to the DLY_EN_OUT2 pin, elapses
before turning on the next enable output, OUT2, in the
ENABLE OUT2 state.
If the 1.8 V supply does not rise to the UV level before the
blanking time elapses, sequencing immediately stops and the
state machine enters the SET FAULT state.
The same scheme is implemented with the other output and
input pins. Every supply turned on via an output pin, OUTx, is
monitored via an input pin, VINx, to check that the supply has
risen above the UV level within the blanking time before the
state machine moves on to the next supply.
When a supply is on and operating correctly, the ADM1186
continues to monitor it for the duration of the power-up
sequence. If any supply drops below its UV threshold level
during a power-up sequence, sequencing stops and the state
machine enters the SET FAULT state.
When the state machine is in the WAIT START state, or at any
time during a power-up sequence, a falling edge on the
DOWN
pin (ADM1186-1) or the UP/
DOWN
pin (ADM1186-2) generates
a fault.
The PWRGD pin is asserted high, independently of the state
machine, when all four VINx pins are above their UV threshold.
The state machine in the ADM1186-1 indicates that the power-
up sequence is complete by asserting the SEQ_DONE pin high.
OPERATION IN POWER-UP DONE STATE
When the power-up sequence is complete, the state machine
remains in the POWER-UP DONE state until one of the
following events occurs:
• A falling edge occurs on the
DOWN
(ADM1186-1) or
UP/
DOWN
(ADM1186-2) pin, initiating a power-down
sequence.
• An undervoltage condition occurs on one or more of VIN1
to VIN4, generating a fault.
• A rising edge occurs on the UP pin, generating a fault
(ADM1186-1 only).
• An external device brings the
FAULT
pin low, causing a
fault (ADM1186-1 only).
POWER-DOWN SEQUENCING AND MONITORING
When the ADM1186 is in the POWER-UP DONE state, a
falling edge on the
DOWN
or UP/
DOWN
pin initiates a
power-down sequence (see
Figure 30 or Figure 32).
The state machine moves to the DISABLE OUT4 state, bringing
the OUT4 pin low and switching off the 3.3 V regulator. A time
delay, set by the capacitor on the DLY_EN_OUT4 pin, elapses
before the state machine moves to the DISABLE OUT3 state.
This sequence of steps is repeated until all four regulators
are switched off and the device is in the WAIT START state.
Because the ADM1186-2 does not have a DLY_EN_OUT1 pin,
there is no delay between the OUT1 pin being brought low and
the state machine returning to the WAIT START state. When
the device is in the WAIT START state, the SEQ_DONE pin is
brought low.
During a power-down sequence, the state machine monitors the
supplies that are still on. If a supply drops below its UV threshold
before it is turned off, the power-down sequence immediately
stops and the state machine enters the SET FAULT state.
A rising edge on the UP or UP/
DOWN
pin during a power-
down sequence generates a fault.
The PWRGD pin is asserted low, independently of the state
machine power-down sequence, when one or more of the
VINx pins drops below 0.6 V.
INPUT GLITCH FILTERING
The VINx, UP,
DOWN
, and
FAULT
inputs on the ADM1186-1
and the VINx and UP/
DOWN
inputs on the ADM1186-2 use a
time-based glitch filter to prevent false triggering. The glitch
filter avoids the need to use some of the operating supply range
to provide hysteresis on an input. This helps to maximize the
available operating supply range for a system, which is especially
important in systems where low supply voltages are being used.
The VINx inputs use a positive glitch filter that is approximately
five times longer than the negative glitch filter. This provides
additional glitch immunity during the power-up sequence as a
supply is rising, but still allows for a quick response in the event
of an undervoltage event on an input.
FAULT CONDITIONS AND FAULT HANDLING
During supply sequencing and operation in the POWER-UP
DONE state, the ADM1186 continuously monitors the VINx,
UP,
DOWN
, and UP/
DOWN
pins for fault conditions. The
FAULT
pin on the ADM1186-1 is monitored to detect external
faults generated by other devices, which is important during
cascade operation.
The following faults are internally generated:
• A supply fails to reach the UV threshold within the time
defined by the BLANK_DLY capacitor during a power-up
sequence.
• A UV condition occurs on VINx after the blanking time
has elapsed during a power-up sequence.
• A UV condition occurs on VINx before the supply is
disabled during a power-down sequence.
• A falling edge occurs on the
DOWN
or UP/
DOWN
pin
during a power-up sequence or in the WAIT START state.
• A rising edge occurs on the UP or UP/
DOWN
pin during a
power-down sequence or in the POWER-UP DONE state.
