OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADM1186-1ARQZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
Data Sheet ADM1186
Rev. B | Page 3 of 28
During a power-up sequence, the state machine enables each
power supply in turn. The supply output voltage is monitored to
determine whether it rises above the UV threshold level within
a user defined duration called the blanking time. If a supply
rises above the UV threshold, the next enable output in the
sequence is turned on. In addition to the blanking time, the
user can also define a sequence time delay before each enable
output is turned on.
The ADM1186-1 provides an open-drain pin, SEQ_DONE,
that is asserted high to provide an indication that a power-up
sequence is complete. The SEQ_DONE pin allows multiple
cascaded ADM1186-1 devices to perform controlled power-up
and power-down sequences.
During a power-down sequence, the enable outputs turn off
in reverse order. The same sequence time delays used during
the power-up sequence are also used during the power-down
sequence as each enable output is turned off; no blanking time
is used during a power-down sequence. At the end of a power-
down sequence, the SEQ_DONE pin is brought low.
During sequencing and when powered up, the state machine
continuously monitors the part for any fault conditions. Faults
include a UV condition on any of the inputs or an unexpected
control input. Any fault causes the state machine to enter a fault
handler, which immediately turns off all enable outputs and
then ensures that the device is ready to start a new power-up
sequence.
The ADM1186-1 has a bidirectional pin,
FAULT
, that facilitates
fault handling when using multiple devices. If an ADM1186-1
experiences a fault condition, the
FAULT
pin is driven low,
causing other connected ADM1186-1 devices to enter their own
fault handling states.
The ADM1186-1 is available in a 20-lead QSOP package, and
the ADM1186-2 is available in a 16-lead QSOP package.
07153-004
POWER-DOWN
DONE
WAIT START
FAULT HANDLER
SEQUENCE
SUPPLY 1 ON
SEQUENCE
SUPPLY 1 OFF
SEQUENCE
SUPPLY 2 ON
SEQUENCE
SUPPLY 2 OFF
SEQUENCE
SUPPLY 3 OFF
SEQUENCE
SUPPLY 4 OFF
SEQUENCE
SUPPLY 3 ON
SEQUENCE
SUPPLY 4 ON
POWER-UP DONE
SEQUENCE UP
TRIGGER
SEQUENCE DOWN TRIGGER
FAULT CONDITION OCCURS
IN ANY STATE
Figure 2. Simplified State Machine Diagram
ADM1186 Data Sheet
Rev. B | Page 4 of 28
SPECIFICATIONS
V
VCC
= 2.7 V to 5.5 V, T
A
= −40°C to +85°C; typical values at T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter Min
Typ
Max
Unit
Test Conditions/Comments
VCC PIN
Operating Voltage Range, V
VCC
2.7
3.3 5.5
V
Undervoltage Lockout, V
UVLO
2.46 V V
VCC
falling
Undervoltage Lockout Hysteresis 50 mV
Supply Current, I
VCC
146
210
µA
Steady state; sequence complete
VIN1 TO VIN4 (VINx) PINS
Input Current −25 +25 nA V
VINx
= 0 V to 1 V
−100 +100 nA V
VINx
= 0 V to 5.5 V; V
VINx
can be greater than V
VCC
Input Threshold
1
0.5952 0.6000 0.6048 V
Input Glitch Immunity
Positive Glitch Duration 19.9 26.6 33.2 µs 50 mV input overdrive
Negative Glitch Duration 2.75 4.7 6.6 µs 50 mV input overdrive
UP,
DOWN
, AND UP/
DOWN
PINS
Input Current −100 +100 nA V
UP/
DOWN
= 0 V to 5.5 V; V
UP/
DOWN
can be greater than V
VCC
Input Threshold
1
1.372
1.428
V
Input Glitch Immunity 3.3 6.8 9.7 µs 100 mV input overdrive
2.7 4.9 7.9 µs 1 V input overdrive
DLY_EN_OUTx AND BLANK_DLY PINS
Time Delay Accuracy 5 9 % External capacitor values of 10 nF to 2.2 μF; excludes
external capacitor tolerance
Time Delay Charge Current 14 µA
Time Delay Threshold 1.4 V
Time Delay Discharge Resistor
Ω
OUT1 TO OUT4 (OUTx) PINS
Output Low Voltage, V
OUTL
0.4 V V
VCC
= 2.7 V, I
SINK
= 2 mA
Leakage Current
1 µA OUTx = 5.5 V
V
VCC
That Guarantees Valid Outputs 1 V Output is guaranteed to be either low (V
OUTL
= 0.4 V)
or giving a valid output level from V
VCC
= 1 V, I
SINK
=
30 µA or V
VCC
= 1.1 V, I
SINK
= 100 µA
PWRGD PIN
Output Low Voltage, V
PWRGDL
0.4 V V
VCC
= 2.7 V, I
SINK
= 2 mA
Leakage Current
1 µA PWRGD = 5.5 V
V
VCC
That Guarantees Valid Outputs 1 V Output is guaranteed to be either low (V
PWRGDL
= 0.4 V)
or giving a valid output level from V
VCC
= 1 V, I
SINK
=
30 µA or V
VCC
= 1.1 V, I
SINK
= 100 µA
FAULT
PIN
Input Threshold
1
1.372 1.4 1.428 V
Input Glitch Immunity 3.1 5.6 8.1 µs 1 V input overdrive
Output Low Voltage, V
FAULT L
0.4 V V
VCC
= 2.7 V, I
SINK
= 2 mA
Leakage Current
1 µA
FAULT
= 5.5 V
V
VCC
That Guarantees Valid Outputs 1 V Output is guaranteed to be either low (V
FAULT L
= 0.4 V)
or giving a valid output level from V
VCC
= 1 V, I
SINK
=
30 µA or V
VCC
= 1.1 V, I
SINK
= 100 µA
Data Sheet ADM1186
Rev. B | Page 5 of 28
Parameter Min
Typ
Max
Unit
Test Conditions/Comments
SEQ_DONE PIN
Output Low Voltage, V
SEQ_DONEL
0.4 V V
VCC
= 2.7 V, I
SINK
= 2 mA
Leakage Current
1 µA SEQ_DONE = 5.5 V
V
VCC
That Guarantees Valid Outputs 1 V Output is guaranteed to be either low (V
SEQ_DONEL
= 0.4 V)
or giving a valid output level from V
VCC
= 1 V, I
SINK
= 30 µA
or V
VCC
= 1.1 V, I
SINK
= 100 µA
RESPONSE TIMING Includes input glitch filter and all other internal
delays
VINx to PWRGD
VINx Going Low to High 21.9 28.8 35.2 µs 50 mV input overdrive
VINx Going High to Low 5.8 7.3 8.9 µs 50 mV input overdrive
VINx to
FAULT
, OUTx Low
VINx Going High to Low (UV Fault) 6.1 7.5 9.2 µs 50 mV input overdrive
UP,
DOWN
, and UP/
DOWN
to
FAULT
,
OUTx Low, t
UDOUT
5.5 8.6 12.1 µs 100 mV input overdrive
5.8 7.7 10.5 µs 1 V input overdrive
External
FAULT
to OUTx Low 10 µs 1 V input overdrive
Fault Hold Time 35 44 54 µs U P, UP/
DOWN
held low
1
Input comparators do not include hysteresis on their inputs. The comparator output passes through a digital glitch filter to remove short transients from the input
signal that would otherwise drive the state machine.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

ADM1186-1ARQZ

Mfr. #:
Buy ADM1186-1ARQZ
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits Quad VTG Monitor & Sequencer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet